Based upon the industry’s most widely adopted CEVA-XC323 Vector DSP architecture, the CEVA-XC5 DSP vector processor offers the performance, area savings, and power efficiency that system designers demand when implementing a broad range of IoT and M2M communication standards.
The CEVA-XC5 combines highly powerful vector capabilities with a general computation engine to deliver industry-leading performance and exemplary power efficiency for even the most cost-, power-, and die-size-constrained devices. It is ideal for applications where the latest LTE Cat-1 or Cat-M1 standards are used concurrently with Wi-Fi 802.11n, PLC, 802.15.4g, ZigBee/Thread, GNSS, or any other emerging IoT communications standard (including NB-IoT, LPWAN, and Wi-Fi 802.11ah).
Low-power operation is achieved with the Power Scaling Unit (PSU), which enables the CEVA-XC5 to take advantage of new Cat-M1/NB1 features such as Power Saving Mode (PSM) and extended DRX to further reduce power.
The CEVA-XC5 can address a wide range of applications including wear-alone wearables, smart grid, surveillance systems, asset tracking, remote monitoring systems, connected cars, and smart utilities.
Provides a complete memory subsystem, with tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller, message queues, emulation, and profiling modules
- Fully programmable DSP processor architecture
- Extremely powerful computation capabilities
- Scalable and configurable architecture
- Innovative second-generation PSU
- Complete memory subsystem
Low Power LTE for IoT: Ubiquitous Coverage with Extended Battery Life
By 2020, ABI Research predicts that there will be more than 45 billion connected devices worldwide. More than half of these devices will incorporate multiple standards in the same device, such as Wi-Fi, 802.15.4g, GNSS and cellular, including the upcoming ultra- low data rate LTE MTC Cat-M. Some of these devices, such as wearables, will only require a battery life of a few days, but others such as asset trackers will demand a battery life of 5-10 years. So how do system designers address these significantly different challenges, while also meeting the stringent cost and power metrics?