The CEVA-XC12 is the first DSP architecture that offers the raw performance and power efficiency required for multi-gigabit class modems. This flexible architecture with multiple options enables it to be customized, configured, and scaled to address applications such as smartphones and other terminals, advanced and centralized access points, small cells, macro cells and cloud RAN (C-RAN).
- 5G use cases
- LTE-Advanced Pro Evolution
- enhanced Mobile Broadband (eMBB)
- Licensed Assisted Access (LAA)
- MulteFire carrier aggregation
- LTE/Wi-Fi Aggregation(LWA)
- cellular V2X
- Wi-Fi 802.11ax
- WiGig 802.11ad
- Fixed Wireless Access (FWA)
- Virtual Reality (VR) systems
CEVA-XC12 is underpinned by a host of technology advances, including a new micro-architecture to meet high frequency requirements and ultra-low power consumption. The CEVA-XC12 can operate at 1.8 GHz in 10 nm while using 50% less power than its predecessor, the CEVA-XC4500. Massive computation capabilities enable it to maintain a high bit rate via the use of quad-vector processor engines, which approach 1 Tera-operations per second (TOPs) performance.
Unique high-precision arithmetic achieves optimal resolution with up to 256×256 dimension matrix processing. Specialized instructions boost all baseband processing components, and new core streaming interfaces facilitate ultra-low latency transfers between cores or accelerators. A control plane for massive-user management and for multi-RAT (Radio Access Technology) systems incorporates a Scalar Processing Unit (SPU) with a CoreMark/MHz score of 4.4, and is designed to handle the huge number of users required for LTE MTC and 5G IoT.
Designed to meet the demanding requirements of extreme multi-gigabit communications use cases
- Core features:
- Fully programmable DSP architecture incorporating unique mix of VLIW and SIMD vector capabilities
- 14-stage pipeline enables very high speed for the most extreme use cases
- 8-way VLIW provides optimal hardware utilization
- Extremely powerful vector processor supports fixed- and floating-point operations with 128 MACs per cycle
- Unique high-precision arithmetic – up to 256x256 dimension matrix processing and non-linear operators
- Fully redesigned CPU/DSP SPU with optimizing C compiler for protocol, control, and DSP native C code supports very low overhead RTOS multi-tasking with dynamic branch prediction.
- Massive number of IoT/MTC users served by control plane
- System features:
- Core streaming interfaces support ultra-low latency
- AMBA 4 compliant matrix interconnect
- Comprehensive multicore support with ACE-compliant cache coherency
- Hardware/software partitioning delivers exceptional power efficiency while maintaining software flexibility with Queue and Buffer Managers and FIC interfaces