The CEVA-TL410 DSP core is based on, and compliant with, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.

Primarily intended for ultra-low power, always-on audio, and sensing DSP applications in voice activation, audio CODECs, and low-power audio chips, the CEVA-TL410 DSP core offers the smallest die size with its single 32×32-bit MAC, dual 16×16-bit MAC, and direct memory interface. It is ideally suited to always-on and always-listening applications within smartphones and smart consumer products.

All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other, as well as with previous-generation CEVA-TeakLite family cores.

An audio instruction set architecture (ISA) provides dedicated audio instructions in all CEVA-TeakLite-4-based cores. All CEVA-TeakLite devices include an integrated, second-generation Power Scaling Unit (PSU 2.0) for smart power management.

The CEVA-TeakLite-4 architecture is scalable to support standalone audio/voice applications including filters, voice pre-processing, audio post-processing, and noise reduction. It also reduces loads on the main CPU for mobile applications by performing multi-channel audio decoding, transcoding, voice pre-processing, and audio post-processing for Android operating systems via the Android Multimedia Framework. The CEVA-TeakLite-4 architecture framework supports user differentiation to allow expansion for handling proprietary algorithm acceleration and future applications.



The CEVA-TL410 DSP is primarily intended for audio applications; however, it is also suitable for a wide range of sensing and natural human-machine interface (HMI) applications.

Ultra-low power and high efficiency
Minimal silicon area for low leakage power and cost-effective implementations
Straightforward instruction set and programming model including a dedicated audio ISA

Main Features

  • Single 32x32-bit MAC
  • Dual 16x16-bit MAC
  • Dedicated audio ISA
  • Second-generation Power Scaling Unit (PSU) for ultra-low power

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