OVERVIEW

PentaG2™ is CEVA’s second generation 5G NR baseband modem IP platform. It is the industry’s only platform offering capable of meeting the extreme performance, low latency and strict power budget requirements of 3GPP 5G UE devices, from high end eMBB to cost effective RedCap (Reduced capability) for the IoT. It leverages CEVA’s unique expertise in DSP and modem architecture from working with world-leading wireless chip and OEM vendors.

The PentaG2™ architecture is a heterogeneous compute platform containing advanced scalar and vector DSP processors and special purpose accelerators, constituting complete signal path inline acceleration for all major processing channels to be able to meet the demanding power envelope of battery powered devices.

PentaG2™ supports the full gamut of 5G eMBB, URLLC, Sidelink and RedCap use cases, for both mmWave and sub-6 GHz, as well as legacy LTE and Cat 1 technologies. The platform is highly scalable and flexible and sustains bit-rates from a 100Mbps in case of the low power IoT, to 10Gbps and above for case of handset eMBB and FWA.

PentaG2™ comes in two main configurations:

PentaG2-Max – targeting wideband eMBB use cases in handsets and CPE/FWA Terminals and mmWave, as well as URLLC enabled AR/VR and C-V2X use cases.

PentaG2-Lite – supports a range of reduced capability use cases, from LTE Cat1, to future 3GPP Rel-17/18 NR RedCap (Reduced capability, aka NR-Lite). PentaG2-Lite is an extremely efficient and lean baseband implementation with complete processing chain acceleration and utilizing a small footprint DSP controller, to meet the most stringent power budgets.

 

PentaG2 circle diagram

Benefits

Fully configurable IP platform for 5G NR and multi-mode RAT.
Dedicated and optimized Max configuration for eMBB and Lite configuration for emerging cellular IoT modems.

Reduces 5G NR modem design time-to-market and lowers entry barriers
Optimal HW/SW partitioning for competitive power budget, using complete acceleration of all major processing chains
Single architecture supporting the full range of 5G NR (and legacy LTE) use cases and operating modes

Main Features

  • Hardware components:
    • Optimized HW accelerators for all processing chains
    • Bit Modulation (BMU) and Bit Demodulation (BDU) units , for complete symbol domain to FEC processing
    • Equalizer and MAC processing unit (EMU) for matrix operations
    • Complete FEC encoding and decoding for both 5G and 4G
    • Other optimized PentaG2 HW accelerators, including: FFT/IFFT engine, Vector MAC Unit (VMU), AI Processor, MLD, HARQ, and more
    • Enhanced CEVA-XC4500 DSP with 5G ISA Extensions
    • CEVA-BX2 scalar DSP for PHY control
  • Software components:
    • Drivers for all HW accelerators
    • 5G and DSP SW libraries running on CEVA-XC4500 and CEVA-BX2 DSPs
    • Complete SW implementation of all major processing chains, including PDSCH, PUSCH, and PDCCH
  • HW and SW Development Kit:
    • System-C SoC simulator supporting all PentaG2 components, allowing fast solution dimensioning, pre-silicon SW development, and PoC. Easy integration to 3’rd party frameworks (e.g. Matlab and OAI)
    • FPGA development board
  • Product notes:

Block Diagrams

PentaG2-MaxPentaG2_max block diagram

PentaG2-Lite

PentaG2 Lite block diagram