Industry’s Most Comprehensive 5G Baseband Platform IP for Mobile Broadband and IoT PentaG2™ is CEVA’s second generation 5G NR baseband modem IP platform. It is the industry’s only...
Industry’s First Comprehensive 5G Baseband Platform IP for 5G RAN ASICs and Open RAN
Building on more than a decade of leadership in baseband IP solutions, in mass production in Tier 1 OEM ASICs for several generation, PentaG-RAN™ is targeting a wide range of cellular infrastructure baseband SoC sockets, from Small Cell to Basestation’S DUs (Distributed Unit) and vDUs (Virtual DU), from Macro Radio Units to Massive MIMO, supporting all Open RAN and O-RAN architecture splits. It has been designed to significantly reduce the entry barriers for companies seeking to break into the new market opportunities available with RAN disaggregation and Open RAN equipment.
The PentaG-RAN™ is a heterogeneous compute platform using optimal HW/SW partitioning allowing inline acceleration of all processing chains and signal chains computing using a rich set of flexible HW accelerators, and mapping all advanced algorithms (e.g. channel estimation, MMSE or beamforming weight calculation) to best in class baseband vector DSPs. This HW/SW partitioning allows scaling up the solution to massive MIMO dimensions with un-matched efficiency and cost. Each workload is mapped to a tuned and optimal processing engine.
PentaG-RAN™ platform addresses both base station and radio compute configurations:
- Base station, supporting Macro DU/vDU and Small Cell – offering a scalable compute platform for L1 inline DU/vDU acceleration. This configuration handles the complete acceleration of the main processing chains (data and control), for both symbol-to-bit domains (including FEC) and frequency processing (including FFT and equalization). Advanced algorithms including channel estimation and MMSE calculation are mapped to the CEVA-XC DSP for optimal processing and power efficiency. It includes a powerful resource pool for accelerating COTS platforms and supports high-PHY and low-PHY 7.2x split partitioning based on Open RAN specifications.
- Radio, supporting Open RAN Low-PHY, Massive MIMO and Beamformer – offering a scalable compute platform for Massive MIMO beamforming processing on RRU side, including Beamformer and Beamforming weight calculation. This configuration offers unmatched compute and PPA efficiency, enabling customers with a competitive path for cost reduction and integration options with transceivers, compared to FPGA and other COTS solutions. It supports a range of use-cases from Small Cell and Macro, to Massive MIMO 32TR to 64TR and beyond, for both Sub-6 and mmWave and supports O-RAN 7.2x splits.
To further expedite time-to-market for PentaG-RAN licensees, the platform is supported by CEVA’s new Virtual Platform Simulator (VPS), a unified System-C modeling environment that allows pre-silicon software development, solution dimensioning, architecture proof-of-concept, and modeling of all platform components. The VPS also includes reference software implementation for main processing chains, as well as beamforming use cases.
PentaG-RAN allows customers to differentiate their products with the inclusion of their own proprietary hardware and algorithms, which are combined with the various processing elements within PentaG-RAN. To further reduce design risk and expedite ASIC design, CEVA can collaborate with customers beyond the PentaG-RAN platform as IP to co-create the entire PHY subsystem or design the complete chip using CEVA-Intrinsix design services.
Fully configurable comprehensive IP platform for 5G NR and multi-mode RAT addressing both Basestation and Radio Open RAN use cases
Reduces 5G NR baseband SoC design time-to-market and lowers entry barriers
Optimal HW/SW partitioning for competitive power budget, using complete acceleration of all major processing chains, allowing efficient scale-up to Massive MIMO dimensions
Heterogeneous compute platform using best in class vector DSPs and rich set of tuned accelerators and processing engines
- Hardware components:
- Optimized HW accelerators for all processing chains
- Bit Modulation (BMU) and Bit Demodulation (BDU) units , for complete symbol domain to FEC processing
- Equalizer and MAC processing unit (EMU) for matrix and beamforming operations
- Complete FEC encoding and decoding for both 5G and 4G
- Other optimized HW accelerators, including: FFT/IFFT engine, Vector MAC Unit (VMU), AI Processor, MLD, HARQ, and more
- World’s strongest CEVA-XC16 vector baseband DSP
- CEVA-BX2 scalar DSP for PHY control
- Software components:
- HW and SW Development Kit:
- Virtual Platform Simulator (VPS) - System-C simulator supporting all PentaG-RAN components, allowing fast solution dimensioning, pre-silicon SW development, and PoC. Easy integration to 3’rd party frameworks (e.g. Matlab and OAI)
- FPGA development board