CEVA-BX2 is a multipurpose hybrid DSP and Controller, designed for the inherent low power requirements of DSP kernels with high-level programming and compact code size requirements of a large control code base.
The CEVA-BX2 addresses intensive workloads such as 5G PHY control, multi-microphone beamforming and neural networks for speech recognition, with up to 16 GMACs per second.
CEVA-BX2 uses quad 32X32-bit MACs and octal 16X16-bit MACs, with enhanced capability for supporting 16×8-bit and 8×8-bit MAC operations.
The CEVA-BX2 is using an 11-stage pipeline and 5-way VLIW micro-architecture, it offers parallel processing with dual scalar compute engines, load/store and program control that reaches a speed of 2 GHz at a TSMC 7nm process node using common standard cells and memory compilers.
The CEVA-BX2 Instruction Set Architecture (ISA) incorporates support for Single Instruction Multiple Data (SIMD) as well as optional floating point units for high accuracy algorithms.
The CEVA-BX2 is accompanied by a comprehensive software development tool chain, including:
- Advanced LLVM compiler
- Eclipse based debugger
- DSP and neural network compute libraries
- Neural network frameworks support
- Real Time Operating Systems (RTOS)
CEVA-BX2 combines low power DSP kernels execution with powerful control capabilities and compact code size
- Octal 16x16 MACs
- Quad 32x32 MACs
- 5-way VLIW
- 8/16/32/64-bit data types
- 16x8 and 8x8 Neural Network support
- Half and single precision IEEE floating point units
- Innovative Branch Target Buffer minimizing branch overhead
- Hardware loop buffer for reduced power consumption of code loops
- High performance controller
- 4.5 CoreMark/MHz
- Dynamic branch prediction
- Full RTOS support
- Compact code size
- Advance system control
- Automatic Queue and Buffer management mechanisms to integrate co-processors and create a cluster of CEVA-BX cores
- Dedicated HW accelerator ports