The CEVA-X2TM is an advanced DSP/controller aimed at high-end multi-standard cellular baseband applications. It has been specifically designed to tackle mobile broadband Physical Layer (PHY) control and other modem functionalities.

The CEVA-X2 is based on a VLIW/SIMD architecture with a 10-stage pipeline operating at 2GHz in typical conditions of a 16nm process.

Other key features include:

  • 4.5 CoreMark/MHz score,
  • quad 16×16 MAC operations per cycle,
  • dual 32×32 MAC operations per cycle,
  • 64-bit SIMD fixed-point operations,
  • Up to two IEEE single-precision floating-point units operating in parallel.

The processor includes two Scalar Processing Units (SPUs), which support 8/16/32/64-bit data types for arithmetic and logic operations. It supports both static branch prediction and optional dynamic branch prediction, and offers both supervisor and user modes.

At a system level, the CEVA-X2 includes a 2-way or 4-way set-associative data cache with write-through and write-back policies, as well as hardware and software pre-fetch capabilities.

Data traffic is managed by CEVA-X2 optional CEVA-Connect mechanism, which ensures intelligent scheduling for high Quality of Service (QoS) and low latency data transfer tasks and minimizes CEVA-X2 processor load.


A fully featured DSP/controller with an advanced VLIW/SIMD architecture that is part of the scalable CEVA-X family

Inbuilt Power Scaling Unit (PSU 2.0) ensures power optimization for prolonged battery life
High-throughput DSP addresses complex wireless communication applications
CEVA-Connect schedules data transfers to hardware accelerators and peripherals, which frees the processor for higher-level tasks

Main Features

  • Unified DSP/controller with two SPUs
  • Flexible data plane processing with 8/16/32/64-bit native C data type support
  • Highly efficient controller with a 4.5 CoreMark/MHz score
  • Advanced Instruction and Data cache architecture with ACE coherency support

Block Diagram

CEVA-X2 Block Diagram