Design Automation Conference, SAN FRANCISCO, Calif., July 24, 2006 - Virage Logic Corporation (Nasdaq: VIRL), a pioneer in Silicon Aware IP™ and leading provider of semiconductor intellectual property (IP) platforms, and CEVA, Inc. (Nasdaq: CEVA; LSE: CVA), the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry, announced today that Virage Logic’s Area, Speed and Power (ASAP) Memory™ High-Speed (HS) memory IP has been adopted by CEVA for global use in its CEVA-XS™ based system platforms.
Virage Logic’s ASAP Memory HS is designed for high-performance applications, making it the perfect choice for the CEVA-XS platforms, including the CEVA-XS1200, which targets mobile multimedia applications such as high-end multimedia phones, personal media players (PMPs) and mobile TVs, and the CEVA-XS1102, which targets 3.5G/HSDPA handsets, WiMax/WiBro terminals and Smartphone applications. CEVA-XS is a family of low-power, highly integrated DSP system platforms designed to reduce development costs and time-to-market for customers designing next-generation DSP-powered devices. Built around the industry-leading CEVA-X DSP cores, the CEVA-XS platforms use industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip.
The ASAP Memory HS’s high-performance architecture begins with the design of its bit cells, which are optimized for fast signal propagation, with the lowest possible bit-line coupling for very high stability. Proprietary circuit design techniques, including high-speed sense amplifiers, fast clocking and fast bit-line recovery contribute to achieving the high speeds required by today's high-performance applications.
“Virage Logic’s highly differentiated IP was chosen for its ability to help us maximize the performance of our CEVA-XS DSP Platforms,