San Jose and Irvine, CA - 23 September 2003 - ParthusCeva, Inc.
(Nasdaq: PCVA, LSE: PCV), the industry's leading licensor of Digital
Signal Processor (DSP) cores and solutions, and AXYS® Design Automation,
Inc., the leading provider of multi-core verification solutions, today
announced the availability of the new MaxLib® Teak® cycle-accurate model
for system architecture trade-off analysis, hardware/software
co-verification and early software development of multi-core designs
incorporating ParthusCeva's licensable Teak DSP Core.

The high-performance cycle-accurate Teak model is fully verified
against the golden RTL reference and integrated into AXYS' MaxSim™
Developer Suite and ARM's RealView debugger for system-level virtual
prototyping and debugging of multi-core System-on-Chip designs combining
Teak DSP cores, ARM cores and associated peripherals. The MaxLib Teak
model was developed and fully verified in record time using AXYS' MaxCore®
technology and the LISA language.

"The new ParthusCeva - AXYS Design models for improved system design
methodology strengthen our licensees capabilities to develop complex
multi-core chipsets faster and more cost-effectively," commented Eyal
Ben-Avraham, VP Support and Embedded Software, DSP division of
ParthusCeva. "With multi-core platforms incorporating our SmartCores™ DSP
family, high performance virtual models are an important element in system
architectural trade-off analysis, hardware and software design
considerations and simultaneous verification for our DSPs."

"With the newest MaxLib Teak model we have once again proven our strong
dedication to ParthusCeva's industry leading DSPs, and continued our
leadership as the premier provider of DSP verification solutions," said
Vojin Zivojnovic, President & CEO of AXYS Design Automation. "The
increasingly complex task of partitioning embedded software between
multiple cores requires efficient system-level virtual prototyping
solutions in order to fully optimize the designs and its software, pass
rigorous verification tests and meet tight development schedules. Our
MaxSim, MaxLib and MaxCore tools are natively developed to help the
designers facing such challenges."

System-level virtual prototypes are available to embedded software
developers and verification teams prior to implementation of the actual
hardware. In contrast to classical hardware based debugging, they uniquely
enable non-intrusive access to internal registers, signals and
transactions at all times during simulation. Specific test scenarios can
be easily reproduced and do not rely on environment conditions. The new
Teak model ensues the successful TeakLite® and OakDSPCore® models; these
models allow ParthusCeva's licensees to fully model systems incorporating
SmartCores and ARM cores in MaxSim.

Teak is a 16-bit fixed-point general-purpose licensable DSP core. Teak
is a dual MAC architecture with parallelism capabilities. Designed as a
fully synthesizable soft core, it enables fast process and foundry
migration. The low power Teak DSP design as well as its high performance
makes it suitable to a wide variety of battery-powered portable
applications, including speech and audio processing, multimedia and
wireless communications (2/2.5 and 3G), high-speed modems, and various
embedded control applications.

The MaxLib Teak cycle-accurate model complies with the new joint
ARM-ParthusCeva DSP interface specification. The Teak model allows
ParthusCeva's licensees to fully model systems incorporating Teak and ARM
cores in MaxSim.

About AXYS Design Automation, Inc.

AXYS® Design Automation, Inc. is a provider of fast, accurate, and
integrated processor and SoC (System-on-Chip) C/C++ modeling and
simulation solutions for the development of high software content SoC
devices. The use of AXYS Design's tool suites in the pre silicon phase
substantially shortens the SoC design cycle by enabling early system
integration and embedded software development, thus reducing NRE cost and
time to market. The MaxSim™ Developer Suite enables modeling and
verification of multi-core SoC designs. The MaxCore® Developer Suite is a
toolset for the automatic generation of processor models and software
development tools. MaxLib® is AXYS Design's growing library of models for
popular SoC components. For more information, visit the AXYS Design web
site at http://www.axysdesign.com.

About ParthusCeva

Further information about ParthusCeva

A PDF copy of this press release is also available here

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AXYS, MaxCore and MaxLib are registered trademarks and
MaxSim is a trademark of AXYS Design Automation, Inc. Teak is a registered
trademark of ParthusCeva, Inc., XpertTeak and SmartCores are trademarks of
ParthusCeva, Inc. All other company or product names are the registered
trademarks or trademarks of their respective owners.

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ParthusCeva Safe Harbor Statement

ParthusCeva Safe Harbor Statement Various statements in
this press release concerning ParthusCeva's future expectations, plans and
prospects are "forward-looking statements", which are subject to certain
risks and uncertainties that could cause actual results to differ
materially from those stated. Any statements that are not statements of
historical fact (including, without limitation, statements to the effect
that the company or its management "believes", "expects", "anticipates",
"plans" and similar expressions) should be considered forward-looking
statements. These statements are subject to a number of risks and
uncertainties that could cause actual results to differ materially from
those described, including the following:

• the industries in which we license our
  technology are experiencing a challenging period of slow growth that has
  negatively impacted and could continue to negatively impact our business
  and operating results;

• the markets in which we operate are highly
  competitive, and as a result we could experience a loss of sales, lower
  prices and lower revenue;

• our operating results fluctuate from quarter to
  quarter due to a variety of factors including our lengthy sales cycle,
  and are not a meaningful indicator for future performance

• we rely significantly on revenue derived from a
  limited number of licensees; and

• other risks discussed in "Management's
  Discussion and Analysis of Financial Condition and Results of
  Operations--Factors that Could Affect Our Operating Results," in our
  quarterly report on Form 10-Q for the first quarter of 2003, filed with
  the U.S. Securities and Exchange Commission on May 14, 2003.