SAN JOSE, Calif., Dec. 7 /PRNewswire-FirstCall/ -- CEVA, Inc. [(NASDAQ: CEVA); (LSE: CVA)], a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, today introduced the industry's first integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox™ Software Development Environment, the Application Optimizer allows application developers to easily develop software for CEVA's DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.

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Substantial Performance Advantages Over Other Licensable Solutions

With the addition of the Application Optimizer, the enhanced development environment for CEVA's DSP cores dramatically simplifies the software development process and improves the absolute performance of the target application. As an example, using the standard AMR-NB (Adaptive Multi Rate compression, narrow band) vocoder C reference, the CEVA-X1622 DSP core required just 19 MHz when compiled out-of-the-box (for worst-case frames and streams). In comparison, other licensable solutions require more than 45% higher speed for the same out-of-the-box compiled code.

Algorithm   OOB C code*   C-optimized*   Assembly       Competitor's
                                         optimized *    OOB C code

AMR-NB        19 MHz         15 MHz      12.5 MHz         27.7 MHz
AMR-WB**    41.7 MHz         30 MHz        22 MHz           N/A
G.729AB       14 MHz       10.3 MHz       9.2 MHz           N/A

* Numbers relate to worst-case frames and streams, using standard ITU / 3GPP C reference code

** AMR-WB using 8.85Kbps bit-rate

Vastly Reduced Software Development Time

With the growing complexity of designing a modern SoC architecture, the burden of embedded software development poses the greatest challenge for IC vendors. The effort involved in writing and optimizing software for a given multifaceted system architecture has become the largest bottleneck in the design cycle. The Application Optimizer toolchain along with a number of other key elements in the CEVA-Toolbox™ Development Environment shifts the software design flow to pure C-level and reduces the burden of architecture-specific know-how traditionally required by application developers.

"With today's highly integrated chip designs and the growing complexity of programming these advanced processors, development tools are now the key item for DSP selection," said Will Strauss, founder and president, Forward Concepts. "The addition of a comprehensive end-to-end C level software optimization toolchain for CEVA's DSP cores offers a significant advantage to customers designing DSP applications, eliminating the tedious and time-consuming requirement for Assembly-level optimization."

Key Elements of the Application Optimizer include:

• Project build optimizer: Creates optimized build configurations, simulates and profiles multiple application scenarios based on the customers application and exact system conditions
• DSP and Communication Libraries: C-callable assembly optimized functions, significantly improve performance and development time of DSP and communication applications.
• Application Profiler: A cycle accurate C-level application and memory subsystem profiler
• Scoring based compilation: Results in less than 1:1.5 ratio between out-of-the-box C to optimized assembly

Other integral elements of the Application Optimizer include; post linker optimizer, debugger connectivity for easy migration of algorithms (e.g.: MATLAB), test environment automation.

CEVA Application Optimizer Demonstration

View a video demonstration of the Application Optimizer at http://www.youtube.com/watch?v=R_GbHtF2H-0.

For more information on the Application Optimizer and CEVA-Toolbox™ Development Environment, visit ceva-dsp.com/Toolbox.

Live Webinar

On January 12, 2010, CEVA will host a live webinar introducing the Application Optimizer.

Date & Time: January 12, 2010 at 8:00 a.m. Pacific / 11:00 a.m. Eastern / 16:00 GMT

Title: Optimize your Software Development Flow -- An intelligent C-level development process for modern embedded processors

Overview: In this webinar, we will explore the latest challenges in software development for advanced embedded architectures and propose a practical flow to meet your target performance with minimal risk and shortest development time.

To register for this webinar, please visit http://www.techonline.com/learning/webinar/222000700.

Development Tools and Support

CEVA's DSPs are supported by a robust Development Environment that includes software development tools, development boards, software system drivers and RTOS. The Development Environment is built upon thousands of man-years of knowledge, accumulated since the inception of CEVA's first DSP core in 1991. CEVA's tools and support have been leveraged by thousands of engineers worldwide to produce more than one billion CEVA-powered chips that have shipped to date. The development tools run on Windows and Linux, and are supported by a worldwide customer service team. CEVA DSPs are further complemented by extensive algorithms and applications from CEVA and the CEVAnet third-party development community.

About CEVA, Inc.

Headquartered in San Jose, Calif., CEVA is a leading licensor of silicon intellectual property (SIP) DSP Cores and platform solutions for the mobile handset, portable and consumer electronics markets. CEVA's IP portfolio includes comprehensive solutions for multimedia, audio, voice over packet (VoP), Bluetooth and Serial ATA (SATA), and a wide range of programmable DSP cores and subsystems with different price/performance metrics serving multiple markets. In 2008, CEVA's IP was shipped in over 300 million devices. For more information, visit ceva-dsp.com

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SOURCE: CEVA, Inc.

Web site: https://www.ceva-ip.com/