CEVA Announces Launch And Licensing Of Pioneering CEVA-X DSP Architecture

December 8, 2003

San Jose, CA - December 08, 2003 - CEVA, Inc., (NASDAQ: CEVA;
LSE: CVA), the leading licensor of Digital Signal Processor (DSP) cores
and integrated applications to the semiconductor industry, today announced
the release of a pioneering new DSP architecture called CEVA-X that offers
best-in-class performance, scalability and lowest cost-of-development in
DSP deployment. The first implementation of the CEVA-X architecture, the
CEVA-X1620, is a dual MAC 16-bit fixed point DSP that has already been
licensed to one of the world's top cellular companies to power their next
generation 3G multimedia phones.

"The DSP market is growing at a rate of 25% annually, and CEVA has
positioned itself to capture an increased share of the market by
delivering an architecture that hits new levels of performance, power
efficiency and scalability," said Will Strauss, President of Forward
Concepts, a leading electronics market research firm. "The ability of
CEVA-X licensees to deploy code-compatible cores to each market's
particular characteristics is impressive because it eliminates the time,
cost and expense associated with adoption of new DSP technology for each
one. CEVA's licensees now have a clear migration path within a unified
architecture."

The CEVA-X architecture combines Instruction Level Parallelism (ILP)
with configurable two, four or eight MAC options, 16 or 32-bit data word,
16 or 32 instruction set, and the capability to extend the instruction set
with customer defined co-processors. CEVA-X's innovative reusable
architecture gives customers complete deployment flexibility within a
unified architecture roadmap.

CEVA-X was designed as a fully synthesizable solution (soft-core)
allowing licensees to customize DSPs to individual markets with complete
flexibility in terms of cost, power consumption, clock speed, foundry and
process. CEVA-X DSP cores are supplied with a complete design flow
allowing the licensee to run cost/performance analysis in rapid-time.
CEVA-X also counters the escalating costs of SoC design with the
industry's first truly compiler-driven architecture, enabling designers to
write in high-level languages such as C and C++ and thereby slash
development cost and time-to-market. Licensees are fully supported with
complete tools and development environment.

CEVA-X's market-leading performance has been confirmed in independent
benchmarks by Berkeley Design Technology (BDTI), which showed that the
CEVA-X (X1620 implementation) will be faster than all DSPs in its class.*
CEVA-X family of DSP cores' performance capabilities opens a wealth of new
markets for programmable DSP technology, including software radio, 3G
multimedia phones, multimedia (e.g. H264) processing, VoIP gateways,
broadband modems, and home entertainment products such as DVD, digital TV,
personal video recorders and set-top boxes.

"CEVA-X is a groundbreaking technology bringing unprecedented
performance and scalability to DSP, and a vital component of our product
portfolio that gives our customers a complete end-to-end DSP solution,"
said Chet Silvestri, CEO of CEVA, Inc. "With the early adoption by one of
the world's leading cellular companies, we are confident that CEVA-X will
play a key role in helping us reinforce and consolidate our position as a
global DSP leader."

Scalability, based on the ability to use the same software
code and other infrastructure components with 2, 4 and 8 MAC units,
those supporting 16- and 32-bit instruction widths, and multiple memory
architecture subsystems. Up to eight instruction sets can be issued in
parallel utilizing four different computation clusters, enabling up to
11 billion instructions per second.
High performance, achieved through a unique mix of Very Long
Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD)
architectures. For example, CEVA-X1620 performs 12 times faster than
CEVA's own Teak DSP.
Support for high-level C/C++ programming, coupled with the use
of a highly efficient optimizing compiler that dramatically reduces
development time as well as permitting code to be ported from another
DSP core quickly and efficiently.
Extendibility, enabling licensees to tailor products to their
specifications by adding proprietary instructions and functions with an
open-instruction customizable format. This permits the development of
customized and differentiated products while using a standard DSP
platform.
A complete Integrated Development Environment (IDE) tool chain
for both hardware and software development, including a compiler,
simulator, debugger, profiler, assembler, linker and DSP libraries,
different modular development system boards, a DMA controller, CPU
interfaces, and multiple peripherals and interfaces.
Ultra-low dynamic power consumption, achieved by built-in
dynamic sleep mode mechanisms.
Enhanced by CEVA's portfolio of DSP Centric-IP, including the
Xpert Open Framework environment that enables plug-and-play with CEVA
Xpert Applications including multimedia (audio, image, video), GPS,
VoIP, Bluetooth, and high-speed serial communications.

The release of the CEVA-X architecture and the CEVA-X1620 coincides
with a corporate name change from ParthusCeva, Inc., to CEVA, Inc., that
was announced separately today. CEVA will be hosting a CEVA-X online
technical seminar tomorrow Tuesday December 9th at 10am EST. Visit
www.techonline.com for the live or archived presentation.

16-bit Fixed-Point Dual MAC architecture
Unique mix of
Very Long Instruction Word (VLIW) and Single Instruction Multiple Data
(SIMD)
High frequency
- up to 450 Mhz @ 0.13u worst case process
High DSP
performance. For example:
2 cycle FFT
butterfly
Single cycle
Viterbi Add-compare-select
Up to 8
instructions in parallel
Variable
instruction width (16 or 32-bit) and variable instruction packets

Ultra low dynamic power consumption achieved by a built in
mechanism which shuts off any unnecessary logic
Enable Customer
Extensions
Highly
efficient C/C++ Compiler
Complete set of
software and hardware development tools chain

* "BDTI Benchmarks" is a trademark of Berkeley design
technology. For benchmark results and other information, visit
www.BDTI.com.

Headquartered in San Jose, CEVA (NASDAQ: CEVA and LSE: CVA) is the
leading licensor of DSP cores and integrated applications to the
semiconductor industry. CEVA markets a portfolio of DSP IP in three
integrated areas: CEVA DSPs; CEVA-Xpert Open Framework Environment;
CEVA-Xpert Applications; supported by Xpert-Integration services. CEVA's
products are used in over 60 million devices each year. The company was
formerly known as ParthusCeva, Inc. For more information, visit
ceva-dsp.com.

A PDF copy of this press release is also available here

Various statements in this press release concerning CEVA's
future expectations, plans and prospects are "forward-looking statements",
which are subject to certain risks and uncertainties that could cause
actual results to differ materially from those stated. Any statements that
are not statements of historical fact (including, without limitation,
statements to the effect that the company or its management "believes",
"expects", "anticipates", "plans" and similar expressions) should be
considered forward-looking statements. These statements are subject to a
number of risks and uncertainties that could cause actual results to
differ materially from those described, including the following:

The industries in which we license our
technology are experiencing a challenging period of slow growth that has
negatively impacted and could continue to negatively impact our business
and operating results;
The markets in which we operate are highly
competitive, and as a result we could experience a loss of sales, lower
prices and lower revenue;
Our operating results fluctuate from quarter to
quarter due to a variety of factors including our lengthy sales cycle,
and are not a meaningful indicator for future performance
We rely significantly on revenue derived from a
limited number of licensees; and
Other risks discussed in "Management's
Discussion and Analysis of Financial Condition and Results of
Operations--Factors that Could Affect Our Operating Results," in our
quarterly report on Form 10-Q for the third quarter of 2003, filed with
the U.S. Securities and Exchange Commission on November 13, 2003.