What is Open RAN?
5G infrastructure build-out is happening but we’re still early on the growth curve. It started strong in China and is now picking up in North America and Europe. Equipment today is dominated by five Tier 1 major players: Nokia, Ericsson, ZTE, Huawei and Samsung. Now smaller players are starting to enter the market. Thanks to Open RAN they can aim to provide solutions such as massive MIMO radio units or baseband distributed units, without needing to offer end-to-end solutions, core to antenna, as is the custom today from the Tier 1 players. There’s ample opportunity to differentiate here. Current implementations depend on off the shelf silicon options, typically expensive and power-hungry FPGAs or x86 processors. An ASIC alternative can be higher throughput, lower power, and lower cost, in addition to solution builder’s own value-adds. Opportunities are so ripe for picking we now see companies across the 5G value chain, semiconductor and transceiver vendors, OEMs, Tier1s, ODMs, even telcos getting involved. Each wanting to control their own destiny in this evolution.
Why are ASICs Better for Massive MIMO?
First think about the DU or small-cell component of an Open-RAN implementation, as is available today. A typical implementation will be built on a Layer-1 implementation in software running on an x86 platform, complemented by one or more FPGAs primarily accelerating forward error correction. While flexible, there is limited capability for scaling up performance when all processing chains and workloads run on a general-purpose core. Massive MIMO compounds the problem, requiring support for more parallel channels.
Now consider the radio unit (RU) side of an Open RAN architecture. These are often implemented with high-end (expensive) FPGAs dedicated to beam forming and the digital front-end to the RF transceivers. However, 5G macrocells are now expected to provide massive MIMO support, requiring much higher levels of parallelism (and therefore more FPGAs) to manage many more channels. Again, scaling up performance with off the shelf components cannot meet reasonable cost or power/efficiency targets.
Contrasting Traditional Open RAN Solutions with ASIC Solutions
PentaG-RAN for Massive MIMO 5G RAN
With a well-established legacy as #1 IP vendor for wireless cellular solutions for both UE and infrastructure, CEVA has introduced its second generation PentaG-RAN™ 5G NR baseband modem IP platform. Designed explicitly to meet the extreme performance, latency and power requirement of massive MIMO RAN devices, , this platform is built on our advanced vector and scalar DSP processors and adds multiple tuned HW acceleration engine forfull signal path inline acceleration.
Take first DU/small cell applications. Unlike the traditional COTS solution, this platform can accelerate the complete signal path. While still preserving SDR flexibility for an OEM to customize side-channel calculations like channel estimation. The platform is fully scalable, from small cell deployments in private networks to full macro cells supporting massive MIMO and Virtual RAN implementations. Scalability is enabled by our market-leading CEVA-XC16 vector DSPs clusters, while software control support is provided by our CEVA-BX2 scalar processor. The heterogeneous platform comes with a comprehensive set of signal path accelerators and co-processors and a rich 5G software SDK and libraries.
Now consider an Open RAN radio unit. The PentaG-RAN platform for this application is built around the same proven vector and scalar DSP cores, here handling algorithms like channel estimation and beam forming. Again, the massive compute required for multi antenna signal paths are fully mapped to hardware accelerators, with scalability throughout. A rich software library provides multiple classes of matrix operation in support of beamforming, precoding and other operations. Beam forming tiles can also be embeded in separate chiplets for OEMs planning scalable chiplet implementations.
Turnkey ASIC Design for Massive MIMO Open RAN
We have many customers who are happy to take our IPs and embed them into their designs. But we also understand that OEMs entering this space see their value in software, modules and system services, not necessarily in ASIC design. For them we offer a turnkey collaborative service through our CEVA-Intrinsix group. For such customers we can design and build the complete ASIC, up to physical implementation signoff and test chip. This service can run from architecture through to implementation, together with a complete software stack. The service is collaborative, working closely with customer need to optimize a feature set to target applications, and to suggest further opportunities for differentiation.
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