VLSI Design Manager
Herzelia, Israel
Job Description

VLSI Design Manager with experience in leading 3 design teams


Education: BSc in Electronics engineering/communication system engineer/ Computer Engineering.

Grades: Tel Aviv-82+, Beer Sheva–85+, Technion-81

Language Knowledge: Verilog and system Verilog


2-4 years of experience as a VLSI Designer – including writing and ownership on a complex Verilog blocks for ASIC with tight frequency, area and power requirements. Working on a full design flow from high-level architecture definitions, through micro ARCH , Verilog writing and verification process up to timing closure and STA

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