Are you an experienced VLSI design engineer with proven managerial capabilities and highly passionate about your work?
Then you belong with us!
CEVA is looking for you to join our growing VLSI team.
Here in CEVA we are developing state of the art DSP ASIC projects in A.I, Vision, Wireless and Base-stations area. The VLSI team is responsible for the planning and the implementation of DSP cores and accelerators which are a part of many future products.
As part of this position you will lead a team of experienced designers, and you will work on a full design flow from architecture definition, through micro ARCH, Verilog writing and verification process up to timing closure and STA.
- Minimum 2.1 Honours degree in Electronic Engineering, Computer Science or a related field.
- 8+ years of experience in digital ASIC design, RTL coding (Verilog/VHDL, SVA) and coverage closure.
- 3+ years of experience in leading an ASIC Design Team.
- Good understanding of design techniques for performance, power and/or area optimisations.
- Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
- Experience working with a Multi-International Company.
- Able to travel to customer sites and other CEVA sites.
- Eligible to work in the EU.