Verification Team Leader
Bristol, United Kingdom
Department
VLSI
Job Description
  • Lead the verification team to understand fully the design specification; design a verification environment and interact with design engineers to identify important verification scenarios.
  • Plan and execute a full verification cycle of complex digital designs.
  • Lead the development of tests and the creation of top-level and block-level test-benches, stimulus and coverage metrics.
  • Coordinate the debug process of failing test cases along with the design team.
  • Ensure delivery of verified design blocks for sign-off, meeting defined functionality, performance and coverage requirements.
  • Make a significant contribution to company-wide verification methodologies.
Requirements

Essential Criteria:

  • Minimum 2.1 Honours degree in Electronic Engineering, Computer Science or a related field.
  • 8+ years of experience in verification of ASICs.
  • 3+ years of experience in leading an ASIC Verification Team in verification planning, design of reference models, generators, checkers and monitors, and definition and completion of functional and code coverage.
  • Strong understanding of state of the art verification techniques, including assertion-based, constrained random and metric-driven verification.
  • Significant experience in development of Specman-e, UVM/System-Verilog or similar testbenches.
  • Demonstrable experience with verification management tools and verification regression.
  • Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
  • Able to travel to customer sites and other CEVA sites.
  • Eligible to work in the EU.

 

Desirable Criteria:

  • Experience with formal verification techniques and tools such as Cadence IFV or JasperGold.
  • Experience with gate level simulation, x-propagation, power verification, contention-checking techniques
  • Experience in TCL or PERL/Python scripting languages
  • Experience in the verification of processors, memory sub-systems, AMBA bus systems.
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