Verification Team Leader for VLSI Department
Herzelia, Israel
Department
VLSI
Job Description
As a Verification Team Leader you will be:
  • Responsible for planning and executing a full verification cycle of complex digital design blocks.
  • Lead the team to fully understand the design specification, to design a verification reference model and to interact with design engineers to identify important verification scenarios.
  • Lead the development of tests and the creation of top-level and block-level test-benches.
  • Lead the process to identify and to write all types of coverage measures for stimulus and corner-cases.
  • Coordinates the debug process of test-cases that fail, along with the design team and ensures a delivery of functionally correct design blocks by signing-off all coverage measures in order to complete the defined verification plan.
Requirements

Education: BSc in Electronics engineering from a leading University.

Experience:

  • 3 + years of experience in the Verification of advanced and complex ASIC RTL Designs.
  • 3 + years of experience in leading an ASIC Verification Team in verification planning, design of reference models, generators, checkers and monitors, and definition and completion of functional and code coverage.

Advantages:

  • Experience in: Specman, System-Verilog, Python, Perl & TCL scripts in Linux
  • Experience in processor verification or memory subsystem verification
  • Experience in formal verification technics
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