Senior/Principal Verification Engineer
Bristol, United Kingdom
- IC verification employing state of the art verification methodologies, tools and infrastructure.
- Writing verification plans with reference to the design specifications.
- Development of tests and the creation of top-level and block-level test-benches, stimulus and coverage metrics.
- Debugging of test cases that fail.
- Support delivery of verified design blocks for sign-off, meeting defined functionality, performance and coverage requirements
- Minimum 2.1 Honours degree in Electronic Engineering, Computer Science or a related field.
- 6+ years of experience in verification of ASICs.
- Strong understanding of state of the art verification techniques, including assertion-based, constrained random and metric-driven verification.
- Significant experience in development of Specman-e, UVM/System-Verilog or similar testbenches.
- Demonstrable experience with verification management tools and verification regression.
- Experience in developing and maintaining TCL, PERL or Python scripts.
- Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
- Able to travel to customer sites and other CEVA sites.
- Eligible to work in the EU.
- Experience with formal verification techniques and tools such as Cadence IFV or JasperGold.
- Experience with gate level simulation, x-propagation, power verification, contention-checking techniques.
- Experience in the verification of processors, memory sub-systems, AMBA bus systems.
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