Junior Design Engineer
Belfast, Northern Ireland
Department
VLSI
Job Description
  • Writing block level/micro-architect specifications of modules
  • RTL coding of modules
  • Verification of sub-systems using variety of tools and methodologies

 

Requirements
  • Essential Criteria:
    • a minimum 2.1 Honours degree or higher in electronics (with preference given to MENG)
    • 0-3 years of experience in Verilog-based design and verification for FPGAs or ICs
    • Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
    • Able to travel to customer sites and other CEVA sites
    • Eligible to work in the EU

 

  • Desirable Criteria:
    • 4-5 years of experience in Verilog-based design and verification for FPGAs or ICs
    • Experience in System Verilog
    • Experience in PERL/Python scripting languages
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