Senior/Principal Digital IC Design Engineer
Bristol, United Kingdom
- Writing micro-architecture specifications of modules.
- RTL Verilog coding of modules. Writing design assertions.
- Support of verification teams in coverage closure and the debug of modules and sub-systems.
- Minimum 2.1 Honours degree in Electronic Engineering, Computer Science or a related field.
- 6+ years of experience in digital ASIC design, RTL coding (Verilog/VHDL, SVA) and coverage closure.
- Good understanding of design techniques for performance, power and/or area optimisations.
- Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
- Able to travel to customer sites and other CEVA sites.
- Eligible to work in the EU.
- Good working knowledge of the back end physical design flow for complex ASIC designs.
- Expertise in the design of processors, memory sub-systems, AMBA bus systems.
- Experience with formal verification techniques and tools such as Cadence IFV or JasperGold.
- Assembly level coding for verification and IP integration.
- Use of the synthesisable subset of SystemVerilog for design.
- Experience in state of the art verification techniques, including assertion-based, constrained random and metric-driven verification.
- Knowledge of TCL, PERL and Python scripting languages.
- Experience in linting, x-propagation and clock-domain crossing tools and techniques.
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