Digital IC Design Team Leader
Bristol, United Kingdom
Department
VLSI
Job Description
  • Technical leadership and mentoring of a team of digital designers.
  • Analysis and review of architecture requirements.
  • Module partitioning and writing micro-architecture specifications of modules.
  • RTL Verilog coding of modules. Writing design assertions.
  • Support of verification teams in coverage closure and the debug of modules and sub-systems.
  • Preparation of IP documents for customer releases.
Requirements

Essential Criteria:

  • Minimum 2.1 Honours degree in Electronic Engineering, Computer Science or a related field.
  • 8+ years of experience in digital ASIC design, RTL coding (Verilog/VHDL, SVA) and coverage closure.
  • 3+ years of experience in leading an ASIC Design Team.
  • Good understanding of design techniques for performance, power and/or area optimisations.
  • Team player with excellent communication abilities to liaise with customers and other CEVA design offices.
  • Able to travel to customer sites and other CEVA sites.
  • Eligible to work in the EU.

 

Desirable Criteria:

  • Experience of specifying and reviewing ASIC architecture requirements.
  • Good working knowledge of the back end physical design flow for complex ASIC designs.
  • Expertise in the design of processors, memory sub-systems, AMBA bus systems.
  • Experience with formal verification techniques and tools such as Cadence IFV or JasperGold.
  • Assembly level coding for verification and IP integration.
  • Use of the synthesisable subset of SystemVerilog for design.
  • Experience in state of the art verification techniques, including assertion-based, constrained random and metric-driven verification.
  • Knowledge of TCL, PERL and Python scripting languages.
  • Experience in linting, x-propagation and clock-domain crossing tools and techniques.
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