The Backend Engineer is responsible for all physical design aspects from RTL to GDSII in the latest transistor geometries using state-of-the-art EDA tools. The Backend Engineer is responsible for the implementation of complex designs starting from synthesis stage and including PnR, CTS and STA stages in order to meet aggressive QoR targets of frequency, area and power.
Education: BSc in HW engineering or Electronics engineering from one of the following universities
Tel-Aviv, Beer sheva, Technion
Grades: Tel Aviv-82+, Beer Sheva-85+, Technion-81+
2-5 years of experience
Experience in full RTL to GDSII flow , from synthesis to placement, CTS, routing and up to signoff – Equivalence check, STA and IR drop analysis
Experience in the following tools (must) – logic synthesis tool (Genus or DC), backend tool (ICC2 or Innovus) and STA tools
Knowledge in: Calibre (or any other physical verification tool)