| |
|
|
 |
Today's increasing complexity of SoC designs requires that system designers
find ways to verify the design before taping out the actual silicon. Advances
in FPGA technology and the increase of FPGA capacity have made them a
valuable tool in system emulation. Large FPGA capacity, in terms of memory
and gate count, allows the system designers to implement the entire SoC
design into one or more FPGA. ASIC HDL coding style is different than
FPGA HDL coding style. The need to keep ASIC power consumption down and
the need to keep a small silicon area dictates certain HDL coding styles
that do not map well into the FPGA architecture. CEVA-Teak, CEVA-TeakLite
and Xpert-Teak FPGA implementation are available, however, uses the same
HDL as for ASIC designs. CEVA uses dedicated ASIC to FPGA synthesis tools
that allow the user to take a "black box" instantiation of the CEVA-Teak
DSP core and use it in the FPGA. The DSP FPGA implementation is FPGA architecture
friendly and ensures predicted timing and area numbers on the FPGA implementation.
FPGA implementation on CEVA's DSP cores was tested with most of the test
benches that are used in the DSP ASIC flow.
|
