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A Licensable DSP System Platform for Wireless Applications


The CEVA-XS1102 Platform is a low-power, highly-integrated SoC platform designed to reduce development costs and time-to-market for customers who are designing next-generation DSP-powered devices.

Built around the industry-leading CEVA-X1622 DSP core, the CEVA-XS1102 platform uses industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip. Additionally, the CEVA-XS1102 is offering the configurability and reduced area of the CEVA-X1622 DSP, thus delivering an improved system platform compared to its predecessor, the CEVA-XS1100.

The CEVA-XS Platform exploits multiple innovative power-saving techniques such as system modules active only when needed, level-two memory architecture and caching, adjust-able DSP system speed, decentralized interconnect topology and selective hardware/software wake-up events.

CEVA-XS Product Note
For a more in-depth look at the CEVA-XS Platform, Download the CEVA-XS Platform Product Note
( pdf, 73kb)
   
   
 

 

CEVA-XS1102 Target Markets

Advanced Cellular
Communications

VoIP Multi Channel Applications

Servo Controller for Storage Devices

With the addition of off-the-shelf software provided by CEVA and its CEVAnet 3rd Party technology partners, the CEVA-XS Platform suits a wide range of applications such as Communications, Multimedia, VoIP, Storage and more.

The CEVA-XS1102 platform is a low-cost platform optimized for advanced wireless and general purpose DSP solutions.

CEVA-XS Block Diagram

CEVA-XS Block Diagram

TechOnLine Web Seminar

CEVA-XS Platform - A Licensable DSP System Platform for Wireless and Digital Multimedia Applications - Available on demand.
view webcast | more information

 

CEVA-XS1102 Technical Highlights

High Performance VLIW SIMD Architecture with Nine stages pipeline

Concurrent execution of up to 8 instructions in parallel
Tightly coupled Architecture extensions to connect external Hardware
Compiler driven load store orthogonal Architecture
Variable instruction width (16 or 32-bit) and variable length of instruction packets
Special instructions for specific applications accelerations
Internal DMA and Cache Memory Subsystem
Two Levels Memory with Up-to 4G-bytes address space

 

CEVA-XS Product Note
For a more in-depth look at the CEVA-XS Platform, Download the CEVA-XS Platform Product Note ( pdf, 87kb)

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