CEVA SGMII IP provides a low power and robust solution for connecting external Gigabit Ethernet PHY chips to the corresponding MAC layers embedded in a separate SoC, via the Serial GMII interface standard.

By combining the silicon-proven ultra low power CEVA Serialiser/Deserialiser (SerDes) technology with a fully compliant SGMII protocol layer, CEVA SGMII is an ideal solution for applications looking to integrate SGMII ports without relying on a separate clock line to time the data transfer and hence delivers the lowest power and pin budget possible.

The CEVA SGMII platform is currently available on TSMC 0.18uG and TSMC 0.13uG