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CEVA-X1622™

The CEVA-X family of cores is based on CEVA's latest pioneering DSP architecture. This architecture offers best-in-class performance, scalability, and lowest cost-of-development for DSP deployment.

CEVA-X1622 is a member of the CEVA-X DSP family consisting of 16-bit data width and two MAC units. CEVA-X1622 target markets include 3G/3.5G cellular handsets and Software radio, multimode terminals, smartphones, and VoIP Gateways & broadband modems.

High Performance at Low Power Consumption

CEVA-X1622 is a high-performance, low-power, fully synthesizable DSP with enhanced memory architecture including configurable memory size (64KB or 128KB), and configurable memory bank organizations in 2 or 4 blocks. The flexible memory architecture allows the customer to make an optimal cost /performance selection in line with market needs In addition, the CEVA-X1622 core offers a reduced gate count compared to other CEVA-X family members.

CEVA-X1622 Target Markets

	3G/3.5G/HSDPA cellular handsets and Software Radio
	Multimode terminals and smartphones
	VoIP Gateways & broadband modems

CEVA-X1622 Product Note

For a more in-depth look at the CEVA-X1622 DSP Core, Download the CEVA-X1622 Product Note
(

pdf, 372kb)

The CEVA-X1622 DSP has a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption.

Using an area-optimized implementation and On-chip Emulation Module (OCEM) enhancements, the core achieves a significant area reduction compared to the CEVA-X1620, making it ideal for advanced baseband and other mobile applications.

High-level Programming

CEVA-X1622 architecture is compiler-driven, implementing orthogonal instruction set and operands, load/store architecture, byte addressing and simple memory configuration (no X/Y partitioning).

CEVA-X1622 Block Diagram

The Computation and Bit Manipulation Unit is responsible for all DSP computations, and includes four independent functional units: Two 16x16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit.

The Data Address and Arithmetic Unit includes two identical Load/Store Units, responsible for generating all data memory accesses. The Scalar Unit is a 32-bit integer CPU block, supporting arithmetic, shift and bit manipulation operations on 32-bit data types.

The Program Control Unit is responsible for the code flow, including sequential flow, branches, loops and interrupts. The Dispatch Unit analyses instruction packets and dispatches single instructions to the different functional units.

Technical Highlights

	High frequency – over 600 MHz @ 65nm G, worst case process and conditions
	Dual MAC 16-bit fixed point DSP
	Combination of VLIW and SIMD architecture concepts
	Up to 8 instructions issued simultaneously
	Variable instruction width (16/32-bit) and variable length of instruction packets
	Two level memory architecture

	Up to 4G byte addressable memory space
	64K/96K/160K/288K-byte level 1 program space, TCM and cache
	64K/128K-byte level 1 data space, TCM
	Program and data DMAs

	Nine stage pipeline
	All instructions can be conditionally executed

The data memory subsystem supports configurable 64K/128K-byte level 1 data space and up to 4G byte of L2 memory, through an AHB-Lite system bus and a programmable DMA. The program memory subsystem supports 64K/96K/160K/288K-byte level 1 program space, TCM and cache. Using a separate AHB-Lite system bus and a programmable DMA, these can be extended up to 4G byte in L2.

A separate IO space is used for peripherals and slow devices built around the DSP.

Soft Core

CEVA-X1622 design implementations are Soft Core based, allowing the customer to select the optimal operating point in terms of die size, power consumption and performance. In addition, the customer has complete flexibility in selecting the foundry, process (e.g. 0.13µ, 90nm, 65nm) and complementary IPs.

CEVA-X1622 IP incorporates fully automated design flow supporting mainstream EDA tools, significantly shortens time-to-market. CEVA-X1622 design can be ported to an FPGA that can be used for product prototype, system integration, design acceleration and clarification.



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