CEVA-X1620™

Product description

The CEVA-X family of cores is based on CEVA's latest pioneering DSP architecture. This architecture offers best-in-class performance, scalability, and lowest cost-of-development for DSP deployment.

CEVA-X1620 is the first implementation of the CEVA-X DSP family consisting of 16-bit data width and two MAC units. CEVA-X1620 target markets include 3G cellular handsets and Software radio, smart phones / PDAs, Video & Audio processing for mobile devices, VoIP Gateways & broadband modems, and home entertainment (Digital TV, HDTV, PVR, HD-DVD).

High Performance at Low Power Consumption

The CEVA-X1620 architecture has a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption.

SIMD architecture allows single instructions to operate on multiple data elements resulting in code size reduction and increased performance. Low power consumption is also achieved in the CEVA-X1620 by its instructions and dedicated mechanisms such as dynamic and selective units shutdowns and clock slow downs.

The Computation and Bit Manipulation Unit is responsible for all DSP computations, and includes four independent functional units: Two 16x16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit.

The Data Address and Arithmetic Unit includes two identical Load/Store Units, responsible for generating all data memory accesses. The Scalar Unit is a 32-bit integer CPU block, supporting arithmetic, shift and bit manipulation operations on 32-bit data types.

The Program Control Unit is responsible for the code flow, including sequential flow, branches, loops and interrupts. The Dispatch Unit analyses instruction packets and dispatches single instructions to the different functional units.