CEVA-TeakLite™

Product description

CEVA-TeakLite DSP Core is a low power, single Multiply- Accumulate (MAC), 16- bit, Fixed point DSP Core, designed specifically to be embedded in highly integrated Systemon- Chip (SoC) applications. It provides various resources for customization and differentiated configuration such as program and data memory size and type (e.g. RAM, ROM Flash etc), interfaces to DSP related peripherals (DMA, Timer, etc.) and other system interfaces.

CEVA-TeakLite is assembly and binary compatible with its predecessor DSP generation, the widely adopted CEVA-Oak DSP Core, providing leverage on the large installed base of legacy software available for this product and migrate it to higher performance DSP..

The CEVA-TeakLite Core has an advanced set of Digital Signal Processing instructions as well as general microprocessor functions. The core’s programming model and instruction set are designed for straightforward generation of efficient and compact code composed of 16-bit width instructions.

CEVA-TeakLite supports access to 64K-word program memory and can efficiently handle large programs that are needed when the DSP is used for both DSP and control functions. Dedicated mechanisms are implemented supporting real-time operating systems, such as unlimited nesting levels of zerooverhead mechanisms (Block-Repeat and the Repeat instructions) and wide Automatic Context Switching.

The following parallel functioning execution Units comprise the CEVA-TeakLite:

	CBU - Computation and Bit Unit, composed of the Computation Unit (CU) and Bit Manipulation Unit (BMU)
	DAAU - Data Address Arithmetic Unit
	PCU - Program Control Unit
	IDU - Instruction Decode Unit

All other peripheral blocks, which are application-specific logic, can be implemented around the DSP core on the same die.