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CEVA-TeakLite-II

Product description

CEVA-TeakLite-II DSP core is a low power, single Multiply-Accumulate (MAC), 16-bit fixed point DSP core, designed specifically for embedded and highly integrated System-on-Chip (SoC) designs. At a speed of 200 MHz @ 0.13u worst case, the TeakLite-II performance, cost and power consumption presents an attractive metric that is attractive to emerging high volume applications in the consumer and wireless fronts.

CEVA-TeakLite-II is binary compatible with its predecessor DSP generations, the widely adopted CEVA-TeakLite and CEVA-Oak DSP cores, allowing its users to leverage on the existing applications and large installed base of software available for these products and easy migrate it to a higher performance DSP.

 

 

TeakLite-II Target Markets

Cellular handsets
2G - GSM, CDMA, TDMA
2.5G - GPRS, EDGE

Portable audio players

Voice over IP phones

Hard Disk Drives

Optical drivers and servo control
   

CEVA-TeakLite-II is a fully synthesizable (Soft Core), process independent design, allowing customers to select the optimal operating point in terms of silicon area, power consumption and frequency. The DSP can be easily ported to any foundry process and library, enabling licensees full control over fabrication costs.

CEVA-TeakLite-II core has an advanced set of Digital Signal Processing instructions as well as general microprocessor functions. The core's programming model and instruction set are designed for straightforward generation of efficient and compact code composed of 16-bit wide instructions. TeakLite-II integrates run time debug functionality useful for field updates and remote fault detections and supports various memory configurations, including RAM, ROM and system peripherals such as DMA, timers, serial ports and bus interfaces.

 

 

CEVA-TeakLite-II Product Note
For a more in-depth look at the CEVA-TeakLite-II DSP Core, Download the CEVA-TeakLite-II Product Note ( pdf, 102kb)

CEVA-TeakLite-II Block Diagram

CEVA-TeakLite-II Block Diagram


Key Benefits

Higher performance for more demanding applications
30% increase in speed compared to
CEVA-TeakLite core
Easy software migration
Fully binary compatible to previous
CEVA DSP cores
Smallest die size DSP, lower cost
Only 0.4 mm2 in 0.13u process
High code compactness, based on 16-bit
instructions only
Excellent support for advanced multi-
function applications
Increased memory space - up to 4M byte
for program and data Combines CPU
and DSP capabilities

 

Technical Highlights
High frequency – up to 200 MHz @ 0.13u worst case process
Low power consumption
Active mode - using full DSP capability
Slow mode - clock speed and current consumption, linearly divided, relative
to active mode by a user-defined
factor
Stop mode - leakage current only
High code density using 16-bit instructions width
   
Note: Frequency depends on configuration, synthesis, foundry, process, operating conditions and libraries.

Development Environment

The CEVA-TeakLite-II is accompanied by the advanced Integrated Development Environment (IDE) based Software Development Tools for embedded applications, supporting Windows, Solaris and Linux operating systems, including

  • Highly optimizing C and C++ compiler
  • Macro assembler and linker
  • Advance Graphic User Interface debugger and simulator
  • Tight MATLAB bi-directional connectivity
  • Integrated graphic application profiler
  • Various utilities and converters

The deliverables include complete and fully automated reference design implementation along with a verification & simulation environments. CEVA-TeakLite-II design can also be ported to an FPGA for prototyping and system integration, prior to taping out the actual silicon.

CEVA-TeakLite-II is backed up by a wide variety of software, applications and algorithms available by CEVA and the CEVAnet third party community.

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