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CEVA-Teak DSP Core is a low power, high performance, dual Multiply-Accumulate
(MAC), 16-bit, Fixed-point DSP core, designed specifically to be
embedded in highly integrated System-on-Chip (SoC) applications.
CEVA-Teak provides interface to program and data memories of different
size and type as well as interfaces to DSP related peripherals,
such as Interrupt and Power management controllers.
CEVA-Teak is binary compatible with the CEVA-TeakLite and CEVA-Oak
DSP Cores, providing leverage on the large installed base of legacy
software available for these products. The CEVA-Teak Core has a
powerful set of DSP instructions as well as general microprocessor
functions.
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The Core’s programming model and instruction set are designed for
straightforward generation of efficient and compact code composed
of 16-bit width instructions in addition to a sub-set of parallel
instructions.
The core has a single-edge clocking system which allows the use
of full- or partial-scan testing methods. The core supports JTAG
emulation, debugging, and testing.
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CEVA-Teak supports access to 4M-word program memory and can efficiently
handle very large programs that are needed when the DSP is used for both
DSP and massive control functions. Dedicated mechanisms were added to
support real-time operating systems, such as unlimited nesting levels
of zero overhead mechanisms (Block-Repeat and Repeat) and advanced Context
Switching capability.
CEVA-Teak is fully synthesizable (Soft Core), process independent design,
allowing the customer to select the optimal operating point in terms of
silicon area, power consumption and frequency. A complete DSP solution,
based on the CEVA-Teak range of deliverables, is offered for reducing
customer’s time-to-market significantly. The deliverables include complete
and fully automated reference design implementation along with a verification
& simulation environments.
CEVA-Teak Block Diagram (click diagram to enlarge)
The CEVA-Teak instruction set includes parallel instructions and supports
32-bit accumulator memory writes in a single cycle.
To achieve high DSP performance, the CEVA-Teak core features dual MAC
operations (executed in a single cycle), fast task-switching, RTOS support,
and more. The core's programming mode and instruction set are designed
for simple generation of efficient and compact code.
A complete CEVA-Teak package includes hardware and software development
tools and a CEVA-Teak EDP (Evaluation and Development Platform) that hosts
a CEVA-Teak development chip.
CEVA-Teak is backed up by a wide variety of software, applications and
algorithms available by CEVA and the CEVAnet third party community.
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Baseband
pdf, 103kb)
CBU -
Computation and Bit Unit, composed of