The CEVA-XC4500 DSP core is the fourth generation of the widely licensed CEVA-XC architecture. Optimized for advanced communication applications, especially high-performance wireless infrastructure equipment, it features a combination of VLIW (Very Long Instruction Word) and vector engines that enhance typical DSP capabilities with advanced scalar and floating-point vector processing.

Based on the architecture of the CEVA-XC4000 DSP family, the CEVA-XC4500 DSP core has two advanced vector-processing units supporting both fixed-point and floating-point instruction sets. Built-in support for traffic management and dynamic scheduling provides efficient data processing within basestations, remote radio heads, and backhaul equipment. Supported by full hardware cache coherency, multiple cores can be deployed to scale the amount of traffic to be handled, from picocells to macrocells to Cloud-RAN, with no software overhead.

With its innovative programmable approach, the CEVA-XC4500 offers the high flexibility needed to support a large number of wireless standards on a single programmable platform, thereby significantly reducing development cost and time-to-market.



An extensive instruction set optimized for a wide range of communications standards enabling rapid implementation of software modems with a minimum of hardware.

Modem design with minimal hardware requirements
Optimized for wireless applications in the high-end smart phone and eNode segments
CEVA-Connect schedules data transfers to HW accelerators and peripherals and frees up the processor for higher-level tasks

Main Features

  • Two Vector Processing (VP) engines
  • Extremely powerful computation capabilities
  • Scalable and configurable architecture
  • Innovative second generation power scaling unit
  • Complete memory subsystem with cache coherent Instruction and Data caches

Block Diagram

CEVA-XC4500 Block Diagram