Overview

The CEVA-XC12 is the first DSP architecture offering the raw performance and power efficiency necessary for multi-gigabit class modems. The flexible architecture with multiple options allows it to be customized, configured and scaled to address applications including smartphones and other terminals, advanced and centralized access points, small cells, macro cells and cloud RAN (C-RAN). It supports all 5G use cases and is well-suited for the design of LTE-Advanced Pro Evolution, enhanced Mobile Broadband (eMBB), Licensed Assisted Access (LAA), MulteFire carrier aggregation and LWA (LTE/Wi-Fi Aggregation), cellular V2X, Wi-Fi 802.11ax, WiGig 802.11ad, Fixed Wireless Access (FWA) and Virtual Reality (VR) systems.

The CEVA-XC12 DSP has been purpose-built from the ground up to solve the most critical challenges of efficiently implementing 5G, LTE-A Pro, MU-MIMO WiFi and other multi-gigabit modems. It is underpinned by a host of technology advances including a new micro-architecture to meet very high frequency requirements and ultra-low power consumption. CEVA-XC12 is capable of operating at 1.8 GHz in 10 nm while using 50% less power than its predecessor, the CEVA-XC4500. Massive computation capabilities enable it to maintain a high bit rate through the use of quad-vector processor engines, which approach 1 Tera operations per second (TOPs) performance.

Unique high-precision arithmetic achieves optimal resolution with up to 256×256 dimension matrix processing. Specialized instructions boost all baseband processing components and new core streaming interfaces facilitate ultra-low latency transfers between cores or accelerators. A control plane for massive-user management and for multi-RAT (Radio Access Technology) systems incorporates a Scalar Processing Unit with a CoreMark/MHz score of 4.4 designed to handle the huge number of users required for LTE MTC and 5G IoT.

 

Benefits

The CEVA-XC12 DSP is designed to meet the demanding requirements of extreme multi-gigabit communications use cases.

Scalable architecture addresses the full range of eNodeB and gNodeB ranging from femtocell, small cell, macrocell RRH to Cloud RAN
Delivers up to 8X more performance and consumes 50% less power than its predecessor
QUAD-vector processor addresses needs of next generation wireless applications

Main Features

  • Core features:
    • Fully programmable DSP architecture incorporating unique mix of VLIW and SIMD vector capabilities
    • 14-stage pipeline enables very high speed for the most extreme use cases
    • 8-way VLIW provides optimal HW utilization
    • Extremely powerful vector processor supporting fixed and floating point operations with 128 MAC per cycle
    • Unique high-precision arithmetic – up to 256x256 dimension matrix processing and non-linear operators
    • Fully redesigned CPU/DSP Scalar Processing Unit with optimizing C compiler for protocol, control and DSP native C code supports very low overhead RTOS multi-tasking with dynamic branch prediction.
    • Massive number of IoT/MTC users served by control plane
  • System features:
    • Core streaming interfaces support ultra-low latency
    • AMBA 4 compliant matrix interconnect
    • Comprehensive multicore support with ACE compliant cache coherency
    • Hardware-software partitioning delivers exceptional power efficiency while maintaining software flexibility with Queue and Buffer Managers and FIC interfaces

Block Diagram

CEVA-XC12 Block Diagram

5G NR base-stations redefine the SDR paradigm

How CEVA-XC12 solves the daunting computing and latency challenges of 5G NR