The CEVA-TL410 DSP core is based on, and compliant with, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.

Primarily intended for ultra-low power, always-on audio and sensing DSP chips used to implement voice activation, audio CODECs and low power audio chips, the CEVA-TL410 DSP core offers the smallest die size with its single 32×32-bit MAC, dual 16×16-bit MACs, and direct memory interface. It is ideally suited to always-on listening applications within smartphones and smart consumer products.

All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other and with previous generation CEVA-TeakLite family cores.

An audio ISA (instruction set architecture) provides dedicated audio instructions in all CEVA-TeakLite-4-based cores. All TeakLite devices include an integrated, second-generation Power Scaling Unit (PSU 2.0) for smart power management.

The CEVA-TeakLite-4 architecture is scalable to support stand-alone audio/voice applications including filters, voice pre-processing, audio post-processing, and noise reduction; also for mobile applications such as reducing load on the main CPU by performing multi-channel audio decode, transcoding, voice pre-processing, and audio post-processing under the Android operating systems, using the Android Multimedia Framework. The CEVA-TeakLite-4 architecture framework also supports user differentiation to allow expansion for handling proprietary algorithm acceleration and future applications.


The CEVA-TL410 DSP is primarily intended for audio applications yet is suitable for a wide range of sensing and natural human-machine interface (HMI) applications.

Ultra-low power and high efficiency
Minimal silicon area allows low leakage power and a cost effective implementation
Straightforward instruction set and programming model including dedicated audio ISA

Main Features

  • Single 32x32 bit MAC
  • Dual 16x16 bit MAC
  • Dedicated audio ISA
  • 2nd generation Power Scaling Unit for ultra-low power

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