CEVA DSP
 
CEVA is the world's leading licensor of DSP, Comms and Multimedia solutions CEVA Digital Signal Processors - DSP
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CEVA / 3rd Party Software
 
 

Mentor Graphics (Tools) 

 

CEVA Tools Partner 

Mentor Graphics (Tools) logo
     

 

   

Seamless® Hardware/Software Co-Verification
 
 

CEVA DSP Cores Supported

     Partnering in Market Solutions For:


CEVA-TeakLite
CEVA-Teak
CEVA-X1620 (PSP coming soon)

      Wireless Handsets
      Portable Multimedia
      Home Entertainment
      Voice over IP
 

About Mentor Graphics (Tools)

Mentor Graphics ® is a technology leader in electronic design automation (EDA), providing software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. The company offers innovative products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design. Mentor Graphics has the broadest industry portfolio of best-in-class products, and is the only EDA company with an embedded software solution.

 

Product Offering

Mentor Graphics® Seamless® co-verification environment enables software/hardware development and verification in parallel, removing software from the critical path, reducing the risk of hardware iterations, shortening design cycle time and increasing overall product quality. Increased visibility into your hardware design allows you to debug designs while they are exercised by production software running on the CEVA DSP and companion CPUs.

Mentor is partnering with CEVA to provide multi-core multi-simulation tools to enable smart and powerful design methodologies for CEVA cores. Seamless allows first-time system design and implementation benefiting the CEVA user community by improving time-to-market for products based on System-on-Chip (SoC) architectures.

Seamless Product Benefits

  • Seamless supports both multi-processor homogeneous and heterogeneous environments. This enables hardware/software co-verification of systems containing both DSP and MCU/MPU cores.
  • Shortens the design cycle time by one to three months for embedded systems - SoC and System-on-Board.
  • Dynamic detail-performance flexibility during verification helps ensure first-pass silicon success.
  • Patented optimizations deliver high-performance and comprehensive design validation.
  • Accurate measurement of key design performance parameters, such as bus, memory and software performance.
  • Collaboration between hardware and software design teams yields optimal system solutions.

 

www.mentor.com/seamless

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