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CEVA LVDS-Serdes IP is a multi-purpose, flexible, low-power Serialiser/
Deserialiser IP core. It provides the foundation physical-layer
IP for many serial communication protocols across a wide data rate,
from 250Mbps to 1.25Gbps, depending on which PLL is instantiated.
The serdes integrates all required elements, including PLL, serializer,
deserializer and clock & data recovery (CDR) logic. It requires
no external components and may be used with customer own or 3rd
party LVDS IO cells. The serdes may also be used with alternative
IO cells, such as LVPECL e.g. for interfaces with optical transceivers.
In addition to providing the basic PMA function for standards
such as 1000Base-X Gigabit Ethernet, it also provides a clock
output on the serial interface at half the line rate (i.e. DDR style).
This is particularly useful for SGMII applications where
some legacy devices may not be capable of extracting the embedded
clock from the data stream.
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