Verification Team Leader for VLSI Department
Herzelia, Israel
Department
VLSI
Job Description

The Verification Team Leader is responsible for planning and executing a full verification cycle of complex digital design blocks. The Verification Team Leader leads his/her team to fully understand the design specification, to design a verification reference model and to interact with design engineers to identify important verification scenarios. The Verification Team Leader leads the development of tests and the creation of top-level and block-level test-benches. The Verification Team Leader leads the process to identify and to write all types of coverage measures for stimulus and corner-cases. The verification Team Leader coordinates the debug process of test-cases that fail, along with the design team and ensures a delivery of functionally correct design blocks by signing-off all coverage measures in order to complete the defined verification plan.

Requirements

Education:
BSc in HW engineering or Electronics engineering from one of the following universities

Tel-Aviv, Ben-Gurion, Technion

Grades: Tel Aviv-82+, Ben-Gurion-85+, Technion-81+, Bar-Ilan 85+

Experience:

3 or more years of experience in the verification of advanced and complex ASIC RTL Designs

3 or more years of experience in leading an ASIC verification team in verification planning, design of reference models, generators, checkers and monitors, and definition and completion of functional and code coverage

Advantages:

Experience in: Specman, System-Verilog, Python, Perl & TCL scripts in Linux

Experience in processor verification or memory subsystem verification

Experience in Formal Verification technics

 

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