Logic Design/Verification Engineer for VLSI Department
Herzelia, Israel
Department
VLSI
Job Description

Verification Engineer will be developing verification environments or for Logic designing for the VLSI team

Requirements

Education: BSc in HW engineering or Electronics engineering from one of the following universities

Tel-Aviv, Beer sheva, Technion

Grades: Tel Aviv-82+, Beer Sheva-85+, Technion-81+

Experience:

0-5 years of experience in Advanced ASIC RTL Design (not verification component)

Advantages:

  • Knowledge in: Verilog & simulation, perl & TCL scripts, Linux
  • Experience in processor design or memory subsystem design
  • Experience in low power technics in RTL level
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