CEVA-SAS
CEVA-SAS IP for Enterprise Storage Systems
The enterprise storage industry remains heavily committed to the SCSI protocol. Driven by ever-increasing requirements for higher performance and higher reliability at a competitive cost, this industry is rapidly evolving from parallel SCSI and Fibre Channel to Serial Attached SCSI (SAS). With a highly efficient full duplex line rate of 6Gbps, SAS 2.0 is the preferred choice for new SAS products designs.
The CEVA-SAS 2.0 Controller IP provides both Target and Initiator functionality. It supports a rich set of features including SCSI SBC-2 End-to-End Protection (DIF), high performance, full duplex DMA with IEEE 1212.1 Scatter/Gather, narrow and wide port support, programmable Initiator address range to support virtual machines and many more.
Reflecting the system complexities of SAS, it provides a comprehensive configuration, control and alarm / status monitoring interface with extensive metric counters and error injection facilities. With complete programmable control for Vendor Specific features, the CEVA-SAS 2.0 Controller IP enables customers to create highly differentiated and robust SAS 2.0 products.
The CEVA-SAS 2.0 Controller IP is suitable for deployment in ASICs, ASSPs, and also the latest generation FPGAs with embedded SERDES technology.
CEVA-SAS IP Target Applications
Target applications for CEVA-SAS2.0 Controller IP include SSDs on the Target side and NAS/ SAN/ Enterprise blade servers on the Initiator side.
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Deliverables |
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SAS2.0 Target (SSP/SMP) and Initiator (SSP/SMP/STP) Controller IP Solutions
Flexible PHY Control Layer provides ease of integration with industry leading PHY/SERDES IP, such as Snowbush and Mosys
Supports SCSI SBC-2 End-to-End Protection (DIF)
Full duplex DMA with IEEE 1212.1 Scatter/Gather for high throughput performance
Programmable Initiator address range to support virtual machines
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Datasheet; Verilog RTL Source Code; Example Software drivers
Simulation Test Environment and User’s Guide
Synthesis Guidelines Document; Example scripts for Synthesis, STA, and LEC
FPGA-based Development System emulating simple SSD (for use with Target Controller IP) or Host HBA (for use with Initiator Controller IP)
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| ...and many more - Download the CEVA-SAS Product Brief for more information |
Architectural Highlights
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A comprehensive and flexible PHY Control Layer to interface to multiple PHY/SERDES options, incorporating 8B/10B coding, OOB processing, programmable Gap / Burst parameters, with support for SNW 1 2 and 3 and SAS Phy TRAIN TRAIN_DONE sequence.
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Independent clock domains on data path and control path for SoC architecture flexibility.
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Comprehensive configuration, control and alarm / status monitoring, with extensive metric counters and error injection facilities
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Designed to support both Narrow and Wide Port SAS implementations.
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Multiple optimizations implemented for high throughput performance, including flexible auto-Response options, interleaving Data with XFER_RDY/Response and Command/Task.
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