|Platforms & Solutions|
The CEVA-TeakLite-4 DSP Architecture for High-Performance, Low-Power Audio and Voice-Processing Applications
The CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based architecture, the CEVA-TeakLite family combines small die size, high code density, and high processing power.
The fourth generation of the CEVA-TeakLite family, the CEVA-TeakLite-4 is a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework. The CEVA-TeakLite-4 is a fully synthesizable, process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.
The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 DSP cores are based on, and compliant to, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.
With a primary target of standalone audio DSP chips used to implement audio CODECs, audio D-Class amplifiers, and noise-reduction chips, the ultra-low-power CEVA-TL410 audio DSP core offers the smallest die size with its single 32x32-bit MAC, dual 16x16-bit MACs, and direct memory interface. If higher performance is required, the CEVA-TL411 audio DSP core provides dual 32x32-bit MACs and quad 16x16-bit MACs.
Alternatively, for CPU-centric SoCs, such as the application processors and main SoCs used in smartphones, digital televisions (DTVs), set-top boxes (STBs), and game consoles, the CEVA-TL420 audio DSP augments the features of the CEVA-TL410 with data and instruction cache controllers and a master/slave AXI system interface (the CEVA-TL421 augments the CEVA-TL411 with the same high-end capabilities). All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other and with previous generation CEVA-TeakLite family cores.
An audio ISA (instruction set architecture) providing dedicated audio instructions is present in all CEVA-TeakLite-4-based cores. Also, all members of the family include an integrated, second-generation Power Scaling Unit (PSU 2.0) for smart power management.
The CEVA-TeakLite-4 architecture is scalable to support stand-alone audio/voice tasks such as filters, voice pre-processing, audio post-processing, and noise reduction; also for mobile applications such as off-loading the main CPU by performing multi-channel audio decode, transcoding, voice pre-processing, and audio post-processing under the Android or Windows 8 operating systems. The CEVA-TeakLite-4 architecture framework also supports user differentiation to allow expansion for handling proprietary algorithm acceleration and future use-cases.
The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 audio DSP cores are supported by a wide range of deliverables, which significantly reduces risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TeakLite-4-based designs can also be implemented in an FPGA for prototyping and system integration.
The CEVA-TeakLite-4 is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’s DSP cores and Platforms and Solutions. Visit our CEVAnet Partners page for more information.
CEVA-TeakLite-4 Target Applications
Target applications for the CEVA-TeakLite-4 DSP cores are primarily audio and voice processing in mobile, home, and automotive products in chips ranging from the smallest, lowest-power audio CODECs, to application processors, to home audio, including digital televisions (DTVs), set-top boxes (STBs), game consoles, and more.