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Highly powerful, multi-mode communication processor for IoT wireless applications

The sixth generation of the widely licensed CEVA-XC architecture, the CEVA-XC5 is optimized for IoT communication applications, 802.11n, PLC, 802.15.4g, GNSS as well as other connectivity applications. The CEVA-XC5 delivers highly powerful vector capabilities alongside a general computation engine to supply the performance and flexibility demanded by various IoT communication applications, while meeting the strict demands for power efficiency and low cost.

CEVA-XC5 applications and use-cases

Target applications for the CEVA-XC5 include:

Multi-Mode IoT Devices with Cellular M2M

  • XC5 supports M2M devices that require multiple communication standards to run concurrently and include cellular based M2M communication such as:
    • LTE MTC with data-rates from 50Kbps to 1Mbps (LTE Cat-0, Cat-M, NB-IoT) and legacy 2G/3G (HSPA, WCDMA, TD-SCDMA, GSM/GPRS/EDGE)
    • Mesh NAN: PLC (G3, IEEE 1901.2, Prime) and 802.15.4g (WiSUN)
    • Low bit rate LAN (WiFi 802.11n 1x1/11ah)
    • Positioning (GNSS, OTDOA)
  • These cellular enabled Devices are used by all M2M market segments which include wearalone wearables, smart grid, smart city surveillance systems, asset tracking, remote monitoring systems, connected cars, smart utilities, etc

Use Case Examples

  • Connected Car w/o Voice
  • Supporting the combination of LTE-CAT-0 or legacy 2G/3G and GNSS
  • Smart Grid Node
  • Supporting a combination of one of each ot the following communication technologies
    • PLC (G3, IEEE 1901.2 and Prime)
    • 802.15.4g (WiSUN)
    • WiFi 802.11n
  • Asset Tracking
  • Supporting the combination of GNSS with LTE-CAT-0 or legacy 2G/3G

CEVA Dragonfly 2 Platform for multi-mode communication IoT wireless applications

The primary objective of the CEVA Dragonfly™ 2 reference platform is to accelerate the design of low-data-rate machine-to-machine (M2M) and IoT communication SoC and applications, for the CEVA-XC5 use cases listed above.
The CEVA Dragonfly 2 multifunction platform is architected around the CEVA-XC5 DSP cores and accompanied by the hardware and software components required to rapidly design machine-type communications (MTC) systems. The platform supports existing and emerging LTE MTC releases (Cat-0, Cat-M),, LPWAN standards (e.g. NB-IoT, EC-GPRS, LoRa, SiGFox, Ingenu), in addition to Wi-Fi 802.11n, GNSS or any other IoT-related communications standard set to be deployed for M2M communication.
CEVA Dragonfly 2 offers system developers a flexible platform that allows for optimal hardware/software system partitioning, combining a low power vector communication DSP with a range of hardware co-processors. Such partitioning enables the software flexibility essential for upgradability and long service life of typical M2M devices, while delivering the power efficiency required to support extended battery life of up to ten years.

CEVA Dragonfly HW/SW Platform

The CEVA Dragonfly 2 reference platform includes the following SW components:

  • LTE MTC Cat-0 PHY Reference–C
    • Software upgradable to Cat-M
  • LTE PHY Libraries
  • GNSS Software
  • LTE-OTDOA Reference-C
  • Protocol Stacks
  • WiFi 802.11n 1x1 PHY and MAC
    • Software upgradable to 802.11ah
  • Smart Grid 802.15.4g Reference-C
  • Smart Grid PLC Reference-C

CEVA Dragonfly 2 Hardware Architecture

The CEVA Dragonfly 2 reference platform includes the following hardware components:

  • CEVA-XC5 DSP Processor
  • HW accelerators
    • Radio Controller
    • Multi-radix FFT and DFT
    • FEC decoders including Viterbi, Turbo and LDPC
    • WiFi 802.11n MAC accelerators
  • CEVA XC Silicon based development board with FPGA (for HW accelerators) equipped with LTE and GNSS Radios

CEVA-XC5  Block Diagram

Features Benefits
Fully programmable DSP architecture incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
  • Vector Communication Unit
  • General Computation Unit
Optimized for wireless applications and offering an extensive instruction set optimized for a wide range of communication standards to enable software-defined modem implementation
Highly powerful vector processor supporting various fixed-point flavors
  • Over 100 16-bit operations in a cycle
Optimized to address the processing requirements for a wide range of next generation wireless applications
High performance architecture
  • 1.3GHz @ 28nm process
  • 16 16-bit fixed-point MACs
  • Variable 16/32-bit instructions
  • 11-Stage pipeline
Enables modem design with minimum hardware requirements
A scalable processor architecture applicable to a wide variety of markets and devices Offers optimal performance to different communication markets requiring high processing capabilities
Optimal hardware-software partitioning via a mix of vector DSP and hardware accelerators Delivers exceptional power efficiency, while maintaining software flexibility
Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
Open architecture and standardized APIs Additional software components can be easily developed or licensed through CEVA’s partners
Complete set of optimized communication libraries including: LTE, 3G, TD-SCDMA, Wi-Fi and more Significantly accelerates multi-mode modem design



The CEVA-XC5 offers a wealth of architectural features as follows:

Fully programmable DSP processor architecture

Vector processing unit operating on 256-bit vector registers offering a powerful SIMD engine

  • Up to 8 simultaneous instructions (8-Way VLIW)
  • Efficient DSP support for non-vectorized data
  • Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

  • 16 16x16-bit MAC operations
  • 32 arithmetic operations per cycle
  • Over 100 16-bit operations in a cycle

Exceptional power efficiency

  • Incorporates Power Scaling Unit – PSU 2.0
  • Dedicated power optimized Tightly Coupled Extensions (TCE)
  • Enhanced power-optimized pipeline

Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules

  • Scalable computation capabilities and memories
  • Configurable utilization of optional instruction sets

Uniquely designed for communication applications

  • High flexibility SIMD programming model with intra-vector permutation capabilities
  • Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more

Tightly Coupled Extensions (TCE)

  • A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including:
    • MLD MIMO detector up to Rank4
    • 3G De-spreader units
    • Fast Hadamard Transform
    • DFT
    • FFT
    • Viterbi decoding
    • LLR processing and HARQ combining
  • User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
  • Offers parallel computing in parallel to the DSP functions
  • Offloading the core and lowering its frequency to minimize power consumption

Complete memory subsystem

  • Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller,, message queues, emulation and profiling modules.
  • Ensures easy integration and optimal performance in Target SoCs

Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices

  • Advanced power management for both dynamic and leakage power
  • Multiple voltage domains associated with the functional units
  • Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO)