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CEVA-XC4500Print this page

Highly powerful and scalable multi-mode communication processor for advanced wireless applications

The fourth generation of the widely licensed CEVA-XC architecture, the CEVA-XC4500 is optimized for advanced communication applications. The CEVA-XC4500 delivers highly powerful vector capabilities alongside a general computation engine to supply the performance and flexibility demanded by next generation communication applications.

CEVA-XC4500 applications and use-cases

Target applications for the CEVA-XC4500 include:

Wireless Terminals

  • Handsets, Smartphones, Tablets, data cards, etc.
  • Supporting: LTE-Advanced, LTE, HSPA/+, W-CDMA, TD-SCDMA, and legacy GSM/GPRS/EDGE

Wireless Cells Baseband Processing

  • Scalable from Pico and Metro Cells up to Macro Cells and Cloud RAN
  • Supporting: LTE-Advanced, HSPA+, TD-SCDMA, Wi-Fi 802.11ac, and more

Wireless connectivity

  • A single platform for: Wi-Fi 802.11a/b/g/n/ac, GPS, and Bluetooth

Enterprise Wi-Fi and WiFi-Cellular Offload

  • Addressing WiFi 802.11ac AP and Small-Cells use cases supporting 3x3, 4x4 and 8x8 MIMO delivering up to 6 Gbps

Wireline modem

  • G.Fast, DSL, VDSL-2, DOCSIS 3.1, and more

Remote Radio Heads (RRH)

  • Targeting digital front-end processing
  • Handling advanced DSP functions including: Digital Pre-distortion (DPD), Up/down sampling Filters, Up/ down conversion, Quadrature Modulation Correction, DC Offset Corrector, Carrier Frequency Offset Corrector and more

Wireless Backhaul

  • Wideband spectrum point-2-point wireless communication supporting up to 4096 QAM
  • Targeting digital front-end processing

CEVA-XC4500 Block Diagram

Features Benefits
Fully programmable DSP architecture incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
  • Vector Communication Units
  • General Computation Unit
Optimized for wireless applications and offering an extensive instruction set optimized for a wide range of communication standards to enable software-defined modem implementation
Highly powerful vector processor supporting fixed and floating point operations
  • Over 400 16-bit operations in a cycle
  • Floating point ISA offering over 40 GFLOPs
Optimized to address the processing requirements for a wide range of next generation wireless applications
High performance architecture
  • 1.3GHz @ 28nm process
  • 64 16-bit fixed-point MACs
  • Variable 16/32-bit instructions
  • 13-Stage pipeline
Enables modem design with minimum hardware requirements
A scalable processor architecture applicable to a wide variety of markets and devices Offers optimal performance to different communication markets requiring high processing capabilities
Comprehensive multicore support
  • Fully featured data cache
  • HW support for cache coherency
  • System interconnect with automated management
  • Dynamic scheduling support
Meets the needs of advanced wireless applications where systems need to offer high flexibility and allow dynamic resource utilization among a large number of cores
Optimal hardware-software partitioning via a mix of vector DSP and hardware accelerators Delivers exceptional power efficiency, while maintaining software flexibility
Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
Open architecture and standardized APIs Additional software components can be easily developed or licensed through CEVA’s partners
Complete set of optimized communication libraries including: LTE-Advanced, LTE, HSPA+, TD-SCDMA, Wi-Fi and more Significantly accelerates multi-mode modem design
...and many more – Download the CEVA-XC4500 Product Brief



The CEVA-XC4500 offers a wealth of architectural features as follows:

Fully programmable DSP processor architecture

Two vector processing units - each unit operates on 256-bit vector registers offering a powerful SIMD engine

  • Up to 8 simultaneous instructions (8-Way VLIW)
  • Efficient DSP support for non-vectorized data
  • Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

  • 64 16x16-bit MAC operations
  • 64 arithmetic operations per cycle
  • Over 400 16-bit operations in a cycle

Unique Vector Floating Point Instruction Set

  • IEEE Single floating comprehensive instruction set enabling user friendly programming in complex communication algorithms

Advanced data cache architecture with Hardware coherency

  • Advanced data cache system supporting HW coherency compliant to latest ACE™ standard from ARM

Exceptional power efficiency

  • Incorporates Power Scaling Unit – PSU 2.0
  • Dedicated power optimized Tightly Coupled Extensions (TCE)
  • Enhanced power-optimized pipeline

Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules

  • Scalable computation capabilities and memories
  • Configurable utilization of optional instruction sets

Uniquely designed for communication applications

  • High flexibility SIMD programming model with intra-vector permutation capabilities
  • Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more

Tightly Coupled Extensions (TCE)

  • A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including:
    • MLD MIMO detector up to Rank4
    • 3G De-spreader units
    • Fast Hadamard Transform
    • DFT
    • FFT
    • Viterbi decoding
    • LLR processing and HARQ combining
  • User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
  • Offers parallel computing in parallel to the DSP functions
  • Offloading the core and lowering its frequency to minimize power consumption

Complete memory subsystem

  • Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
  • Ensures easy integration and optimal performance in Target SoCs

Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices

  • Advanced power management for both dynamic and leakage power
  • Multiple voltage domains associated with the functional units
  • Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO)

LTE-A Ref. Architecture

CEVA-XC4500 multi-mode LTE-Advanced reference architecture

LTE CAT6 -Reference Architecture Based on multiple CEVA-XC processors, CEVA offers a complete multimode LTE-Advanced reference architecture targeting LTE-A REL12 categories. The reference architecture leverages on years of accumulated knowledge with CEVA’s Tier-1 baseband licensees, is based on CEVA-XC optimized communication Libraries and addresses the entire PHY layer requirements.

Reference architecture highlights:

  • A complete LTE-A PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: LTE-Advanced, TD-LTE-Advanced, HSPA+, TD-SCDMA, and more
  • Built around CEVA-XC processors with minimal complementary hardware accelerators
  • Offers industry's most competitive SDR platform in terms of both cost and power consumption
  • Supports maximal throughput of LTE-A Rel-12CAT-12 UE FDD (DL: 600Mbps, UL: 150Mbps) with up to 4x4 MIMO and carrier aggregation of up to four carrier components to a total of 80MHz channel
  • High operating margins enabling customer differentiation by software

Wi-Fi 802.11ac Ref. Architecture

CEVA-XC4500 based Wi-Fi 802.11ac reference architecture

WiFi11ac 8x8 Architecture

Based on a CEVA-XC4500 processors, CEVA offers a complete Wi-Fi 802.11ac reference architecture targeting advanced 8x8 access point(AP).

Reference architectures highlights

  • The majority of the 11ac optional modes
  • All modulation schemes up to 256-QAM: MCS0-MCS9, from one to eight spatial streams
  • 1024-QAM modulation (MCS10 and MCS11)
  • Long Guard Interval (800ns) and Short Guard Interval (400ns)
  • Space Time Block coding (STBC) for improved link reliability, minimizing the effects of scattering, reflection and refraction
  • Low Density Parity Check (LDPC), which improves receive sensitivity by 2-3 dB compared to a Viterbi decoder
  • Transmit beamforming, as a beamformer and as a beamformee
  • Multi User MIMO (MU-MIMO)