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Scalable multicore architecture for a range of mobile devices, home networking and wireless infrastructure, automotive and smart-grid applications

CEVA-XC4210 applications and use-casesThe third generation of the widely licensed CEVA-XC architecture, the CEVA-XC4210 is optimized for advanced communication applications. The CEVA-XC4210 delivers highly powerful vector capabilities alongside a general computation engine to supply the performance and flexibility demanded by next generation communication applications.

Target applications for the CEVA-XC4210 include:

Wireless Terminals

  • Handsets, Smartphones, Tablets, data cards, etc.
  • Supporting: LTE-Advanced, LTE, HSPA/+, W-CDMA, TD-SCDMA, and legacy GSM/GPRS/EDGE

Wireless Infrastructure

  • A scalable solution from Small Cells up to Macrocells

Universal DTV Demodulator and satellite broadband

  • A programmable solution targeting digital TV demodulation in software
  • Target standards: DVB-T, DVB-T2, DVB-S2, ISDB-T, ATSC, DTMB, etc.
  • Supporting satellite broadband in mobile and stationary conditions

Wireless connectivity

  • A single platform for: Wi-Fi 802.11a/b/g/n/ac, GPS, and Bluetooth

Enterprise Wi-Fi and WiFi-Cellular Offload

  • Addressing WiFi 802.11ac AP and Small-Cells use cases supporting  3x3, 4x4 MIMO delivering up to 1.7Gbps

Wireline modem:

  • G.Fast, DSL, VDSL-2, DOCSIS 3.1 and more


  • A single platform for: wireless PAN (802.11, 802.15.4, etc.), PLC (Power Line Communication), and Cellular communication (LTE, W-CMDA, etc.)

CEVA-XC4210 Block Diagram

Features Benefits
Fully programmable DSP architecture incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
  • Vector Communication Units
  • General Computation Unit
Optimized for wireless applications and offering an extensive instruction set optimized for a wide range of communication standards to enable software-defined modem implementation
High performance architecture
  • 1.2GHz @ 28nm process
  • 64 16-bit fixed-point MACs
  • Variable 16/32-bit instructions
  • 11-Stage pipeline
Enables modem design with minimum hardware requirements
A scalable processor architecture applicable to a wide variety of markets and devices Offers optimal performance to different communication markets requiring high processing capabilities
Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
Open architecture and standardized APIs Additional software components can be easily developed or licensed through CEVA’s partners
Complete set of optimized communication libraries including: LTE-Advanced, LTE, HSPA+, TD-SCDMA, Wi-Fi and more Significantly accelerates multi-mode modem design



The CEVA-XC4210 offers a wealth of architectural features as follows:

Fully programmable DSP processor architecture

Two vector processing units - each unit operates on 256-bit vector registers offering a powerful SIMD engine

  • Up to 8 simultaneous instructions (8-Way VLIW)
  • Efficient DSP support for non-vectorized data
  • Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

  • 64 16x16-bit MAC operations
  • 64 arithmetic operations per cycle
  • Over 400 16-bit operations in a cycle

Exceptional power efficiency

  • Incorporates Power Scaling Unit – PSU 2.0
  • Dedicated power optimized Tightly Coupled Extensions (TCE)
  • Enhanced power-optimized pipeline

Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules

  • Scalable computation capabilities and memories
  • Configurable utilization of optional instruction sets

Uniquely designed for communication applications

  • High flexibility SIMD programming model with intra-vector permutation capabilities
  • Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more

Tightly Coupled ExtensionsS (TCE)

  • A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including: MLD MIMO detector, 3G De-spreader units, DFT,  FFT, Viterbi,
  • LLR processing and HARQ combining
  • User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
  • Offers parallel computing in parallel to the DSP functions
  • Offloading the core and lowering its frequency to minimize power consumption

Complete memory subsystem

  • Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
  • Ensures easy integration and optimal performance in Target SoCs

Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices:

  • Advanced power management for both dynamic and leakage power.
  • Multiple voltage domains associated with the functional units.
  • Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO).

LTE-A Ref. Architecture

CEVA-XC4210 multi-mode LTE-Advanced reference architecture

LTE-A Reference ArchitectureBased on multiple CEVA-XC processors, CEVA offers a complete multimode LTE-Advanced reference architecture targeting LTE-A Rel-10 Cat-7. The reference architecture leverages on years of accumulated knowledge with CEVA’s Tier-1 baseband licensees, is based on CEVA-XC optimized communication Libraries and addresses the entire PHY layer requirements.

Reference architecture highlights:

  • A complete LTE-A PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: LTE-Advanced, TD-LTE-Advanced, HSPA+, TD-SCDMA, and more
  • Built around CEVA-XC processors with minimal complementary hardware accelerators
  • Offers industry's most competitive SDR platform in terms of both cost and power consumption
  • Supports maximal throughput of LTE-A Rel-10 CAT-7 UE FDD (DL: 300Mbps, UL: 100Mbps) with up to 8x4 MIMO and carrier aggregation of up to two carrier components to a total of 40MHz channel
  • High operating margins enabling customer differentiation by software

Wi-Fi 802.11ac Ref. Architecture

CEVA-XC4000 based Wi-Fi 802.11ac reference architecture

802.11ac Reference ArchitectureBased on a single CEVA-XC4210 processor, CEVA offers a complete Wi-Fi 802.11ac reference architecture targeting mobile stations (STA). The reference architecture was developed together with Antcor, a member of the CEVA-XCnet partner program and addresses the entire PHY and lower MAC layers requirements.

Reference architectures highlights:

  • Addresses both PHY and Lower-MAC with minimal complementary hardware acceleration
  • Built around a single CEVA-XC4210 processor with minimal complementary hardware accelerators
  • Offers industry's most competitive SDR platform in terms of both cost and power consumption
  • Supports up to full 160MHz channel bandwidth
  • Maximal throughput of 867Mbps (scalable to 1.7Gbps) with up to 4x2 MIMO beam-forming, with 256-QAM support
  • Extremely low power solution targeting low power process for mobile Wi-Fi stations (STA)
  • High operating margins enabling customer differentiation by software