CEVA-XC4000
A Low-Power DSP Architecture Framework for the Widest Array of Advanced Wireless Standards including LTE-Advanced, Wi-Fi 802.11ac, DVB-T2 and more
 The CEVA-XC family of DSP cores features a combination of VLIW (Very Long Instruction Word) and Vector engines that enhance typical DSP capabilities with advanced vector processing. Based on the architecture of the CEVA-X DSP family, the CEVA-XC family of DSP cores incorporates up to four modular Vector Communication Units into the CEVA-X framework. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors targeting the most demanding wireless applications and use cases, enabling software-defined modem design with minimal hardware. With its innovative programmable approach, the CEVA-XC family offers high flexibility that supports a large number of wireless standards on a single programmable platform, thereby significantly reducing development cost and time to market.
The third generation of the CEVA-XC family, the CEVA-XC4000, offers a series of six processors optimized for advanced communication applications. The CEVA-XC4000 delivers highly powerful vector capabilities alongside a powerful general computation engine supplying the performance and flexibility demanded by next generation communication applications.
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Target applications for the CEVA-XC4000 include:
Wireless Terminals
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Handsets, Smartphones, Tablets, data cards, etc.
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Addressing: LTE, LTE-A, WiMAX, HSPA/+, and legacy 2G/3G standards
Wireless Infrastructure
Wireless connectivity
Universal DTV Demodulator
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A programmable solution targeting digital TV demodulation in software
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Target standards: DVB-T, DVB-T2, ISDB-T, ATSC, DTMB, etc.
SmartGrid
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A single platform for: wireless PAN (802.11, 802.15.4, etc.), PLC (Power Line Communication), and Cellular communication (LTE, WCMDA, etc.)
Others
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White-space, DSL, VDSL, MoCA, DOCSIS, G.hn
Features
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Benefits
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Fully programmable DSP architecture incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
- Vector Communication Units
- General Computation Unit
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Optimized for wireless applications and offering an extensive instruction set optimized for a wide range of communication standards to enable software-defined modem implementation
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High performance architecture
- 1.2GHz @ 28nm process
- Up to 128 16-bit fixed-point MACs
- Variable 16/32-bit instructions
- 11-Stage pipeline
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Enables modem design with minimum hardware requirements
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A scalable processor architecture offered in a series of six DSP cores applicable to a wide variety of markets and devices
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Offers optimal performance to different communication markets requiring high processing capabilities:
- Wireless terminals
- Wireless infrastructures: from femtocells and picocells up to macrocells
- Connectivity
- DTV demodulation
- White-space communication
- …and more…
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Easy software development
- Advanced IDE
- Optimizing C compiler with Vec-C support (dedicated support for vector processors)
- Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
- Macro assembler, linker, and GUI debugger
- RTOS
- Smooth migration path from off the-shelf ASSPs
- MATLAB bi-directional connectivity
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Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
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Open architecture and standardized APIs
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Additional software components can be easily developed or licensed through CEVA’s partners
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Complete set of optimized communication libraries
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Significantly accelerates multi-mode modem design
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The CEVA-XC4000 offers a wealth of architectural features as follows:
Fully programmable DSP processor architecture
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One, two or four vector processing units - each unit operates on 256-bit vector registers offering a powerful SIMD engine
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Up to 8 simultaneous instructions (8-Way VLIW)
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Efficient DSP support for non-vectorized data
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Efficient support for control and ANSI-C operations
Extremely powerful computation capabilities
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Up to 128 16x16-bit MAC operations and/or 64 16x8-bit MAC operations
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Up to 128 arithmetic operations per cycle
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Over 800 16-bit operations in a cycle
Exceptional power efficiency
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Incorporates a new Power Scaling Unit – PSU 2.0
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Dedicated power optimized Tightly Coupled Extensions (TCE)
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Enhanced power-optimized pipeline
Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules
Uniquely designed for communication applications
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High flexibility SIMD programming model with intra-vector permutation capabilities
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Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more
Tightly Coupled Extenstions (TCE)
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A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including: TD-FD transformation, ML MIMO detector, De-spreader and more
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User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
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Offers parallel computing in parallel to the DSP functions
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Offloading the core and lowering its frequency to minimize power consumption
Complete memory subsystem
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Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB3 interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices:
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Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO).
CEVA-XC4000 multi-mode LTE-Advanced reference architecture
Based on multiple CEVA-XC4000 processors, CEVA offers a complete multimode LTE-Advanced reference architecture targeting LTE-A Rel-10 Cat-7. The reference architecture was developed together with mimoOn, a member of the CEVA-XCnet partner program and addresses the entire PHY layer requirements.
Reference architecture highlights:
- A complete LTE PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: TD-LTE-A, HSPA+ Rel-9, TD-SCDMA, WiMAX and more
- Built around CEVA-XC4000 processors with minimal complementary hardware accelerators
- Offers industry's most competitive SDR platform in terms of both cost and power consumption
- Supports maximal throughput of LTE-A Rel-10 CAT-7 UE FDD (DL: 300Mbps, UL: 100Mbps) with up to 8x4 MIMO and carrier aggregation of up to two carrier components to a total of 40MHz channel
- High operating margins enabling customer differentiation by software
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CEVA-XC4000 based Wi-Fi 802.11ac reference architecture
Based on a single CEVA-XC4000 processor, CEVA offers a complete Wi-Fi 802.11ac reference architecture targeting mobile stations (STA). The reference architecture was developed together with Antcor, a member of the CEVA-XCnet partner program and addresses the entire PHY and lower MAC layers requirements.
Reference architectures highlights:
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Addresses both PHY and Lower-MAC with minimal complementary hardware acceleration
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Built around a single CEVA-XC4210 processor with minimal complementary hardware accelerators
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Offers industry's most competitive SDR platform in terms of both cost and power consumption
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Supports up to full 160MHz channel bandwidth
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Maximal throughput of 867Mbps (scalable to 1.7Gbps) with up to 4x2 MIMO beam-forming, with 256-QAM support
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Extremely low power solution targeting low power process for mobile Wi-Fi stations (STA)
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High operating margins enabling customer differentiation by software
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DSP Cores 
