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CEVA-XC323 DSP Core for Advanced Wireless Terminal, Infrastructure and DTV Demodulation Applications

ceva_XCThe CEVA-XC323 architectureThe CEVA-XC family of DSP cores features a combination of VLIW (Very Long Instruction Word) and Vector engines that enhance typical DSP capabilities with advanced vector processing. Based on the architecture of the CEVA-X DSP family, the CEVA-XC family of DSP cores incorporates up to four modular Vector Communication Units into the CEVA-X framework. The scalable CEVA-XC architecture offers a selection of highly powerful communication processors targeting the most demanding wireless applications and use cases, enabling software-defined modem design with minimal hardware. With its innovative programmable approach, the CEVA-XC family offers high flexibility that supports a large number of wireless standards on a single programmable platform, thereby significantly reducing development cost and time to market.

The second generation of the CEVA-XC family, the CEVA-XC323, is a highly powerful processor that is optimized for wireless terminal and infrastructure applications and that has been widely adopted by multiple Terminal and Infrastructure vendors. The CEVA-XC323 offers highly powerful vector capabilities alongside a powerful general computation engine supplying the performance and flexibility demanded by next generation communication applications.

Target applications for the CEVA-XC323

Wireless Terminals

  • Handsets, Smartphones, Tablets, data cards, etc.
  • Addressing: LTE, LTE-A, WiMAX, HSPA/+, and legacy 2G/3G standards

Wireless Infrastructure

  • A scalable solution for femtocells up to macrocells

Universal DTV Demodulator

  • A programmable solution targeting digital TV demodulation in software
  • Target standards: DVB-T, DVB-T2, ISDB-T, ATSC, DTMB, etc.

Wireless connectivity

  • A single platform for: Wi-Fi 802.11a/b/g/n/ac, GPS, Bluetooth and more

SmartGrid

  • A single platform for: wireless PAN (802.11, 802.15.4, etc.), PLC (Power Line Communication), and Cellular communication (LTE, W-CMDA, etc.)
Features Benefits
Fully programmable DSP incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
  • Vector Communication Units
  • General Computation Unit
Optimized for wireless applications and offering an extensive instruction set optimized for the specific needs of wireless baseband to enable software-defined modem implementation
High performance architecture
  • 1GHz @ 40nm G
  • 32 16-bit fixed-point MACs
  • Variable 16/32-bit instructions
  • 11-Stage pipeline
Enables modem design with minimum hardware requirements
A scalable processor applicable to a wide variety of markets and devices Offers optimal performance to different applications with a clear roadmap for standard evolutions:
  • Wireless terminals
  • Wireless infrastructures: from femtocells and picocells up to macrocells
  • Connectivity
  • DTV Demodulation
  • …and more…
Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
Open architecture and standardized APIs Additional software components can be easily developed or licensed through CEVA’s partners
Complete set of optimized communication libraries Significantly accelerates multi-mode modem design
…and many more – Download the CEVA-XC323 Product Brief for more information

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Highlights

The CEVA-XC323 offers a wealth of architectural features as follows:

Fully programmable DSP

  • Two vector processing units - each unit operates on 256-bit vector registers offering a powerful 512-bit SIMD engine
  • Up to 8 simultaneous instructions (8-Way VLIW)
  • Efficient DSP support for non-vectorized data
  • Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

  • 32 16x16-bit MAC operations and/or 64 16x8-bit MAC operations
  • 64 arithmetic operations per cycle
  • 32 logic operations per cycle
  • 200 16-bit operations in a cycle

Scalable and configurable architecture for use in a wide range of wireless applications and devices through different configurations and optional modules

  • Scalable computation capabilities and memories
  • Configurable utilization of optional instruction sets

Uniquely designed for wireless baseband

  • High flexibility SIMD programming model with intra-vector permutation capabilities
  • Optimized instruction set for wireless modems, including matrix processing, MIMO detectors, filtering, complex data permutations, and bit stream processing

Efficient flow of the entire baseband application

  • Communication operations - Vector communication units deal with vectorizable data
  • General DSP operations - Complete support for general ANSI-C DSP functions, adaptive parameters, etc.
  • Control code - Fully interruptible, conditional ISA, branch prediction, delay slots, etc.
  • Memory accesses - Dual flexible data addressing units with dedicated scalar unit

Complete memory subsystem

  • Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB3 interface, advanced DMA controller, emulation and profiling modules.
  • Ensures easy integration and optimal performance in Target SoCs

Offers a homogeneous multi-core system design capability including:

  • Wide AXI busses for massive data transfers
  • Snooping mechanism to detect external device accesses
  • Message queues allowing synchronization and easy system control;
  • Exclusive access allowing atomic access to external memories,
  • External debug interfaces allowing cross-triggering.

Integrates an innovative Power Scaling Unit (PSU) offering significant energy savings for both battery-operated and stationary devices:

  • Advanced power management for both dynamic and leakage power.
  • Multiple voltage domains associated with the functional units.
  • Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO).

Communication Software

CEVA-XC Communication Libraries

CEVA offers a complete set of DSP and communication libraries optimized for CEVA-XC323 to ease the implementation of software-based wireless modems. CEVA's unique multimode software-defined modem library offering significantly simplifies customer development of multimode modems.

Highlights of the CEVA-XC libraries include:

  • Covers the most critical algorithms and addresses the entire transceiver chain
  • LTE FDD, LTE TDD, HSPA+, and WiMAX are available; additional libraries are in development
  • C-callable optimized DSP code ensuring optimal DSP performance
  • Minimizes required architecture know-how and enables designers to focus on system code and proprietary algorithms
  • A generic implementation that can be configured to address the customer's unique use cases
  • System-independent code ensures smooth integration into the customer SoC

CEVA-XCnet Partner Program

CEVA-XC323 Enabled Products

The CEVA-XCnet Partnership Program is a comprehensive network of strategic third-party technology suppliers that brings together a variety of critical and complementary technologies: communication software and hardware IPs for 3G and 4G applications, DSP software design services, real-time operating systems (RTOS), SoC level prototyping, and simulation tools. CEVA-XCnet members gain in-depth understanding of the CEVA-XC architecture, development environment and libraries, and have a direct link to CEVA's internal R&D resources. Consequently, CEVA-XCnet reduces development costs and risks for CEVA-XC licensees, and significantly accelerates the development of advanced wireless communications solutions.

LTE Ref. Architectures

CEVA-XC based multi-mode LTE reference architectures

CEVA-XC LTE reference architecture

Based on the CEVA-XC323 processor, CEVA offers complete multimode reference architectures targeting both wireless terminals and wireless infrastructure. These reference architectures leverage on years of accumulated knowledge with CEVA’s Tier-1 baseband licensees, are based on CEVA-XC optimized communication Libraries and  address the entire PHY layer requirements.

Reference architectures highlights:

  • A complete LTE PHY system architecture addressing the entire PHY layer requirements of multiple standards in software including: LTE FDD, LTE TDD, and HSPA+
  • Built around CEVA-XC323 processor with minimal complementary hardware accelerators
  • Software upgradable to other baseband standards with clear roadmap for standards evolution
  • Offers industry's most competitive SDR platform in terms of both cost and power consumption
  • Ensures system completeness and fast time to market for CEVA-XC based modem design
  • Takes into consideration MAC and RF interfaces, simplifying integration into customer SoC

DTV Ref. Architecture

CEVA-XC based multi-mode DTV reference architecture

CEVA-XC DTV reference architecture

Based on the CEVA-XC323 processor, CEVA offers a multi-standard DTV demodulation reference architecture. Together with Idea! Electronic Systems, a member of the CEVA-XCnet partner program, the companies have developed a complete, ISDB-T solution based on a multi-standard reference architecture, including ISDB-T software library functions, ISDB-T PHY software IP, a universal front-end engine and FEC accelerators.

Leveraging the fully programmable CEVA-XC DSP, every existing and future DTV demodulation standard can be supported in software rather than hardware, significantly reducing the die size, design complexity and cost of multi-standard DTV demodulation solutions. In addition, the CEVA-XC processor can support any other air interface to further differentiate the product, including LTE, HSPA+ and WiFi.

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CEVA-XC323 Software Development Kit (SDK)

CEVA-XC323 silicon-based SDKCEVA now offers a new silicon-based, software development kit (SDK) for runtime software development based on the CEVA-XC323 DSP. The CEVA-XC323 silicon embedded in the SDK was designed by CEVA and manufactured on a 65nm process, delivering up to 800MHz performance. This level of performance facilitates the design of software-based modems and associated application software, for multiple communication standards, in parallel and in a real-time environment.

The SDK is comprised of:

  • CEVA-XC323 silicon, including CEVA’s innovative Power Scaling Unit (PSU) which enables advanced power management within the SoC. 
  • Two XC-DMA controllers
  • Program cache
  • 512 KB L1 data and 1MB shared L2 memory
  • External 64/128-bit AXI master and slave interfaces
  • 32-bit master APB interface
  • Mltiple efficient master/slave memory interfaces
  • Power Management Unit (PMU)
  • Timers
  • Interrupt Control Unit (ICU)
  • 6.5Gbps optical transceiver
  • Dual port 1Gbps Ethernet
  • 1GB of DDR2 memories
  • 64MB SSRAM memories
  • HDMI in/out ports
  • Dual Serial Rapid IO transceivers
  • Multiple large FPGA modules open for user programmability to add SoC specific logic
  • Comprehensive set of optimized DSP software libraries. 

 The SDK also includes a broad range of standard interfaces, enabling easy integration into customer-specific system designs, and a complete debug, profiling and tracing capabilities in real-time, to enable the modeling of real system conditions well in advance of customer silicon being available. The development kit is supported by CEVA-Toolbox™, a complete software development, debug, and optimization environment.