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CEVA-XC12Print this page

World's most advanced communication DSP, providing cutting-edge performance for multi-Gigabit class connectivity

The fifth generation of the widely licensed CEVA-XC architecture, the CEVA-XC12 is optimized for the most advanced multi-Gigabit communication applications. The CEVA-XC12 delivers the most powerful vector capabilities for data plane processing together with a high performance scalar engine for the most demanding control plane processing required to support multi-RAT and massive number of users.

CEVA-XC12 addressable standards

Target applications for the CEVA-XC12 include:

Wireless eNodeB Cells Baseband Processing

  • Scalable from Femto and Small Cells all the way to Macro Cells and Cloud RAN
  • Supporting: 5G NR, Verizon 5GTF, LTE-Advanced Pro, LAA, LWA, LTE-A, HSPA+, TD-SCDMA, Wi-Fi 802.11ax/ac/ad, and more

Carrier Wi-Fi Access Points

  • Supports: Wi-Fi 802.11ax/ac/ad/n with 8x8 MU-MIMO up to 10Gbps

Enterprise Wi-Fi and Wi-Fi-Cellular LTE Offload

  • Addressing Wi-Fi 802.11ax/ac/ad AP and LTE-A Pro Small-Cells with LAA and LWA supporting up to 8x8 MIMO delivering up to 10 Gbps

Wireline Modem

  • G.Fast, DSL, VDSL-2, DOCSIS 3.1, and more

Remote Radio Heads (RRH)

  • Targeting digital front-end processing
  • Handling advanced DSP functions including: Digital Pre-distortion (DPD), Up/down sampling Filters, Up/ down conversion, Quadrature Modulation Correction, DC Offset Corrector, Carrier Frequency Offset Corrector and more

Wireless Backhaul

  • Wideband spectrum point-2-point wireless communication supporting up to 4096 QAM
  • Targeting digital front-end processing

Fixed Wireless Access (FWA) Terminals

  • xDSL and Cable replacement for Homes, SoHo, Enterprise
  • Supporting: 5G NR, Verizon 5GTF, LTE-Advanced Pro, LTE-A

Mobile Wireless Terminals

  • eMBB Handsets, Smartphones, Tablets, data cards, etc.
  • Supporting: 5G NR, LTE-A Pro, LTE-Advanced, LTE-A, HSPA/+, W-CDMA, TD-SCDMA, and legacy GSM/GPRS/EDGE

CEVA-XC12 Block Diagram

Features Benefits
Fully programmable DSP architecture incorporating a unique mix of VLIW and Vector capabilities using a combination of computational units:
  • Vector Communication Unit
  • Scalar Computation Unit
Optimized for wireless applications and offering an extensive instruction set optimized for a wide range of communication standards to enable software-defined modem implementation
Highly powerful vector processor supporting fixed and floating point operations
  • 920 Vector GOPS
Optimized to address the processing requirements for a wide range of next generation wireless applications
High performance architecture
  • 1.8GHz @ 10nm process
  • 128 fixed-point MACs
  • Variable 16/32-bit instructions
  • 14-Stage pipeline
Enables very high speed for extreme use cases
A scalable processor architecture applicable to a wide variety of markets and devices Offers optimal performance to different communication markets requiring high processing capabilities
Comprehensive multicore support
  • Streaming interface
  • Fully featured data cache
  • HW support for cache coherency
  • System interconnect with automated management
  • Dynamic scheduling support
Meets the needs of advanced wireless applications where systems need to offer high flexibility and offload multi-core and accelerators from the DSP. Dedicated inter-core interface designed for ultra-low latency
Optimal hardware-software partitioning via a mix of vector DSP and hardware accelerators Delivers exceptional power efficiency, while maintaining software flexibility
Easy software development
  • Advanced IDE
  • Optimizing C compiler with Vec-C support (dedicated support for vector processors)
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • RTOS
  • Smooth migration path from off the-shelf ASSPs
  • MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market
Open architecture and standardized APIs Additional software components can be easily developed or licensed through CEVA’s partners
Complete set of optimized communication libraries including: 5G NR, V5GTF, LTE-Advanced Pro, LTE, NB-IoT, HSPA+, TD-SCDMA, Wi-Fi 11ax, Wi-Fi 11ac, Wi-Fi 11n Significantly accelerates multi-mode modem design
...and many more



The CEVA-XC12 offers a wealth of architectural features as follows:

Fully programmable DSP processor architecture

Four vector processing units - each unit operates on 512-bit vector registers offering a powerful SIMD engine

  • Up to 8 simultaneous instructions (8-Way VLIW)
  • Efficient DSP support for non-vectorized data
  • Efficient support for control and ANSI-C operations

Extremely powerful computation capabilities

  • 128 16x16-bit MAC operations
  • 2K-bit memory bandwidth

Unique Vector Floating Point Instruction Set

  • IEEE Single floating comprehensive instruction set enabling user friendly programming in complex communication algorithms

Highly efficient Scalar engine architecture

Four scalar processing units (SPU) – with a total of 8 single cycle MAC operating in SIMD mode

  • Reaches a CoreMark/MHz score of 4.4
  • Dynamic branch prediction
  • Full RTOS support and ultra-fast context switch
  • Highly efficient and compact C Control code
  • Efficient support for control and ANSI-C operations
  • Optional FPU in each SPU

Advanced data cache architecture with Hardware coherency

  • Advanced data cache system supporting HW coherency compliant to latest ACE™ standard from ARM

Scalable and configurable architecture for use in a wide range of wireless communication applications and devices through different processors, configurations and optional modules

  • Scalable computation capabilities and memories
  • Configurable utilization of optional instruction sets

Uniquely designed for communication applications

  • High flexibility SIMD programming model with intra-vector permutation capabilities
  • Optimized modem instruction sets including high precision ISA, ML MIMO detectors, filtering, complex data permutations, and more

Tightly Coupled Extensions (TCE)

  • A selection of coprocessor units allowing efficient low power implementation of demanding transceiver algorithms including:
    • MLD MIMO detector up to Rank4
    • 3G De-spreader units
    • Fast Hadamard Transform
    • DFT
    • FFT
    • Viterbi decoding
    • LLR processing and HARQ combining
  • User-defined coprocessor interface enabling customers to reuse their existing proprietary IP
  • Offers parallel computing in parallel to the DSP functions
  • Offloading the core and lowering its frequency to minimize power consumption

Complete memory subsystem

  • Includes tightly coupled memories (TCM), caches, AXI system interfaces, APB interface, advanced DMA controller, Fast Inter Connect (FIC) buses, message queues, emulation and profiling modules.
  • Include unique control and data planes integrated system to control accelerators and multi-core transfers
  • Ensures easy integration and optimal performance in Target SoCs

Integrates an innovative second generation Power Scaling Unit (PSU 2.0) offering significant energy savings for both battery-operated and stationary devices

  • Advanced power management for both dynamic and leakage power
  • Multiple voltage domains associated with the functional units
  • Multiple operational modes ranging from full operation, to debug bypass, to memory retention, to complete power shut-off (PSO)