CEVA-X1641 DSP core for Multimedia, Baseband and Multi-Channel Voice Applications
The CEVA-X family of cores is based on a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing, thereby providing extended parallelism and low power consumption. The SIMD architecture allows single instructions to operate on multiple data elements, thereby resulting in code size reduction and increased performance. This processor family offers best-in-class performance, scalability, ease of programmability at the C level, and the flexibility to support a wide variety of applications. The CEVA-X family offers an architectural framework from which multiple DSP designs are derived. Each DSP design is aimed to serve different application needs characterized by performance, power consumption, and cost.
CEVA-X1641: High performance CEVA-X processor targeting more-demanding DSP applications. The quad-MAC, 8-way VLIW CEVA-X1641 DSP core offers the performance required for demanding DSP applications.
CEVA-X1641 Target Applications
Target applications for the CEVA-X1641 include multimedia processing and 3G/4G baseband processing in mobile devices, multi-channel voice processing in gateways, and more.
|Advanced VLIW + SIMD architecture offering very high ILP (Instruction Level Parallelism)
||Optimal for demanding DSP applications in various markets|
||Meets the power, cost and frequency requirments of next generation SoCs|
|Easy software development
||Smooth C-level software development and easy integration into the target SoC reduces risk and time-to-market|
|Used to power the CEVA-MM2000 multimedia platform||The fully-programmable CEVA-MM2000 provides a complete multimedia solution – Audio, Video, Imaging, Voice – allowing cost-effective deployment of new products and differentiation through software|
|…and many more – Download the CEVA-X1641 Product Brief for more information|
The CEVA-X1641 is a high-performance, low-power, fully synthesizable DSP with a 16-bit data width and quad 16-bit fixed-point MAC units.
The CEVA-X1641 is based on a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing, thereby providing extended parallelism, as well as low power consumption. The SIMD architecture allows single instructions to operate on multiple data elements resulting in code size reduction and increased performance.
In addition to DSP operations, the CEVA-X1641 provides strong support for control code, thereby reducing cycle count and program size associated with control and overhead code:
- All instructions are conditional with a predication mechanism
- Rich instruction set for bit manipulation
- Branch prediction
- Zero overhead loops
- …and more…
The data memory subsystem is configurable and supports up to 1MB L1 data space. Using a separate AHB-Lite system bus and a programmable DMA, this can be extended up to 4GB in L2. Similarly, the program memory subsystem is configurable and supports up to 1MB L1 program space, TCM and cache. Using a separate AHB-Lite system bus and a programmable DMA, these can be extended up to 4GB in L2.
Codecs available directly from CEVA include:
|Vocoders||Audio decoders||Audio encoders||Video decoders||Video encoder||Imaging|
|G.723||MP3||MP3||H.264 BP||H.264 BP||JPEG decoder|
|G.729||MPEG4 AAC-LC||MPEG4 AAC-LC||H.264 MP||MPEG4 SP||JPEG encoder|
|G.729.1||HE-AAC V1||HE-AAC V1||MPEG4 SP|
|G.711||HE AAC V2||MPEG4 ASP|
|AMR-NB||Dolby Digital (AC3)|
Many other codecs and post-processing functions are available from our CEVAnet partners.
The CEVA-XS1200A: A licensable DSP sub-system for wireless and digital multimedia applications. The CEVA-X1641 DSP core can be augmented with the CEVA-XS1200A sub-system, which offers a rich set of DSP peripherals, interconnections, and interfaces. The CEVA-XS1200A sub-system employs industry-standard system buses, thereby providing designers with the ability to add their own hardware blocks or connect the CEVA-X1641 DSP core to other on-chip systems.
The CEVA-XS1200A sub-system includes:
- A flexible memory architecture enabling memory sharing between the DSP and CPU cores<
- A programmable 3D DMA engine designed for multimedia applications
- Time Division Multiplex (TDM) ports for glue-less connectivity of any standard serial interface<
- A complete set of system peripherals, including timers, an interrupt control unit, a power management unit, and General-Purpose Input/Outputs (GPIOs)
- Interfaces to L2 memories, accelerators, and other on-chip systems.
The combination of the CEVA-X1641 DSP core and the CEVA-XS1200A sub-system results in a complete highly-integrated SoC platform, which significantly reduces risk, cost, and time-to-market for customers who are designing next-generation DSP-powered devices. With the addition of a complete set of optimized multimedia codecs, CEVA offers the CEVA-MM2000, a fully-programmable high-performance engine supporting video, imaging, audio, and voice processing capabilities completely in software.
CEVA-X Announcements18 Jul 2016 CEVA to Unveil its CEVA-X2 DSP at the Linley Mobile & Wearable Conference 2016
23 Feb 2016 CEVA and Spreadtrum Expand Long-Term Partnership for LTE SoCs Targeting Mid and High End Smartphones
17 Feb 2016 Introducing The NEW CEVA-X - The World's Most Efficient Processor Architecture for Baseband Applications
- Products Overview
- DSP Cores
- Connectivity Platforms
- Development Environment