The NEW CEVA-X
Scalable Processor Framework for combined Controller and DSP processors targeting mobile handsets, IoT devices and baseband modems
The NEW CEVA-X effectively combines real-time Controller attributes with DSP capabilities, for applications such as high-end PHY control plane processing, Machine-Type-Communications, Connectivity, and other baseband applications.
The NEW CEVA-X has been designed from the ground up with compiler efficiency in mind in order to yield highly optimized code size and performance with C code straight out of the box or minimal C optimization.
Target applications for The NEW CEVA-XThe NEW CEVA-X target applications and use cases are multifold and span the whole communication field:
- High-end multi-carrier handsets: Baseband controller, PHY datapath controller, Advanced Voice/Audio codecs and pre-processing.
- IoT connectivity devices: Protocol stack and PHY control and datapath for Bluetooth, BLE, WiFi, Zigbee/Thread,
- Machine to Machine (M2M) endpoint devices: Protocol and PHY control and datapath for LTE MTC (Cat-1, Cat-0, Cat-M), LPWAN (NB-IoT, EC-GPRS, LoRa, Sigfox, …), Smart Grid (802.15.4g, PLC)
- Wireless and wireline baseband: Protocol and PHY control and datapath for audio and video satellite standards, G.Fast and other wireline standards.
The NEW CEVA-X FeaturesModern baseband modem controllers require the appropriate balance between three essential capability sets:
- Efficient Control features.
- Powerful DSP features.
- Advanced System Control features.
The NEW CEVA-X framework enables CEVA to design Baseband controllers with a different balance between these three feature sets to address the various requirements of each use case listed above.
For example a high-end smartphone baseband that supports multi-RAT and multi-carrier requires a PHY Controller, that offers both very powerful DSP performance combined with advanced control features, while a Narrow-Band M2M baseband requires a PHY Controller with a very efficient control capabilities but limited DSP performance.
NEW CEVA-X Key features
- Scalable VLIW/SIMD architecture
- Variable length pipeline
- Scalable memory bandwidth (up to 256-bit)
- Fixed and optional floating-point
- Optional Instruction and Data Caches
- Optional Branch Target Buffer
- Optional Traffic Managers (Queue and Buffer)
Key Controller features
- Up to 8 scalar operations per cycle
- Zero latency ISA
- Static and optional dynamic branch prediction
- 32-bit HW division and multiplication (fixed and optional floating-point)
- Fully orthogonal register set
- Ultra-fast context switch
Key DSP features
- Up to eight 16x16 MAC operations per cycle
- Up to four 32x32 MAC operations per cycle
- Up to 128-bit SIMD processing
- Up to four single-precision floating point operations per cycle
- Loop buffer
- Supports 8/16/32/64 bit data types and operations
Key System features
- Optional advanced 4-way cached instruction and data memory subsystem with pre-fetch
- Automatic management of HW accelerators through CEVA-Connect Queue and Buffer Managers
- High throughput system interfaces
CEVA-X4 - Multi-RAT PHY Control Processor
The CEVA-X4 is the first core based on The NEW CEVA-X architecture, targeting the most complex workloads of multi-RAT multi-carrier PHY control and PHY datapath processing in 2G/3G/4G/5G basebands.
CEVA-X2 - Multi-RAT PHY Control Processor
The CEVA-X2 is the second core based on The NEW CEVA-X architecture, targeting the most complex workloads of multi-RAT, multi-carrier PHY control processing in 2G/3G/4G/5G basebands.
CEVA-X Announcements18 Jul 2016 CEVA to Unveil its CEVA-X2 DSP at the Linley Mobile & Wearable Conference 2016
23 Feb 2016 CEVA and Spreadtrum Expand Long-Term Partnership for LTE SoCs Targeting Mid and High End Smartphones
17 Feb 2016 Introducing The NEW CEVA-X - The World's Most Efficient Processor Architecture for Baseband Applications
- Products Overview
- DSP Cores
- Connectivity Platforms
- Development Environment