The CEVA-TeakLite-III DSP Core for High-Volume, Cost-Sensitive HD Audio, Voice, and Baseband Applications
The CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based architecture, the CEVA-TeakLite family combines small die size, high code density, and high processing power.
The third generation member of the CEVA-TeakLite family, the CEVA-TeakLite-III is a low-power, native 32-bit, dual MAC, 10-stage pipeline, fixed-point DSP engine that has been specifically designed to be embedded in highly-integrated System-on-Chip (SoC) devices. The CEVA-TeakLite-III is a fully synthesizable (soft core), process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.
CEVA-TeakLite III Offers Superb Audio DSP Performance
Suitable for the most demanding multi-stream, multi-channel audio processing, the native 32-bit CEVA-TeakLite-III offers superb audio DSP performance. It also offers high performance wireless modem implementations thanks to FFT, Viterbi, and other algorithmic accelerators that are built directly into the core’s Instruction Set Architecture (ISA).
The high-performance, low-power CEVA-TeakLite-III DSP engine forms the basis of the CEVA-TL3210 and CEVA-TL3211 DSP cores. The CEVA-TL3210 offers a wealth of high-end features including a configurable L1 program cache memory and support for industry-standard APB and AHB-Lite system busses. By comparison, the CEVA-TL3211 offers configurable L1 program and data cache memories, support for high-speed AXI system busses, and an integrated Power Scaling Unit (PSU).
CEVA-TeakLite III Supporting Deliverables
The CEVA-TL3210 and CEVA-TL3211 DSP cores are supported by a wide range of deliverables, which significantly reduces risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TL3210 and CEVA-TL3211 designs can also be implemented in an FPGA for prototyping and system integration.
The CEVA-TeakLite-III is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’s DSP cores and Platforms and Solutions. Visit our CEVAnet Partners page for more information.
CEVA-TeakLite-III Target Applications
Target applications for the CEVA-TeakLite-III include HD audio, voice, 2G/2.5G/3G wireless baseband, Power Line Communications (PLC), VoIP, and other signal processing for mobile computing devices, wireless handsets, portable media players, Digital TVs (DTVs), Set-top boxes (STBs), Blu-ray Disc players, and more.
||High performance makes the CEVA-TeakLite-lll applicable to multiple application domains from audio and voice to baseband|
|Native 32-bit, Harvard/SIMD architecture DSP
||Supported by a broad range of fully-certified HD-Audio and voice codecs|
|Easy software development
||Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market|
|...and many more – Download the CEVA-TL3210 and CEVA-TL3211 Product Briefs for more information|
Based on a native 32-bit architecture, the CEVA-TeakLite-lll can perform two 16x16-bit Multiply-Accumulate (MAC) operations or one 32x32-bit MAC in a single cycle. The CEVA-TeakLite-lll also offers:
- Strong bit-manipulation capabilities for stream processing
- Up to three instructions executed in parallel
- Dedicated single-precision and double-precision FFT instructions
- Up to 4GW program memory and 4GW data memory (16-bit words)
- L1 program memory (cache or TCM)
- L1 data memory (CEVA-TL3210 = TCM; CEVA-TL3211 = 2-way, set-associative, hardware-configurable cache)
- See the CEVA-TL3210 and CEVA-TL3211 Product Briefs for more information
The CEVA-TeakLite-lll supports an advanced set of digital signal processing instructions as well as general-purpose microprocessor instructions. The CEVA-TeakLite-lll's instruction set and programming model are designed for the straightforward generation of compact and efficient code.
Support for up to 4GW (16-bit words) of program memory means that the CEVA-TeakLite-III can efficiently handle the large programs that are required when the core is used to handle both DSP and control functions. Similarly, support for up to 4GW (16-bit words) of data memory means that the CEVA-TeakLite-III can handle and process large data buffers.
An integrated Power Scaling Unit (PSU) provides advanced power management including support for clock and voltage scaling (only available with the CEVA-TL3211).
The CEVA-TeakLite-III is backward compatible with its predecessors, including the widely adopted CEVA-TeakLite, CEVA-TeakLite-II and CEVA-Teak DSP cores. This allows new designs to leverage existing applications and a large installed base of software; it also makes it easy for existing designs to be migrated to a higher performance core.
Codecs available directly from CEVA include:
|Vocoders||Audio decoders||Audio encoders||Post-processing|
|G.723||MP3||MP3||Dolby Mobile 3+|
|G.729.1||MPEG4 AAC-LC||MPEG4 AAC-LC||Dolby ProLogic IIx|
|G.711||HE-AAC V1||HE-AAC V1||Dolby Volume|
|G.722||HE AAC V2 7.1||SBC||DTS Extended Surround (ES)|
|AMR-NB xxx||WMA10||Dolby Digital encoder (DDCE)||DTS Neo:6|
|Dolby Digital Plus|
|Dolby Digital (AC3)|
|DTS Master Audio|
|DTS High Resolution|
|DTS Digital Surround|
Many other codecs and post-processing functions are available from our CEVAnet partners.
Either the CEVA-TL3210 or the CEVA-TL3211 DSP cores form the basis for CEVA-HD-Audio, which is a complete high-end audio hardware and software platform for Digital Televisions (DTVs), Set-Top Boxes (STBs), and Blu-ray Disc Players, as well as the audio sub-systems in Application Processors for smartphones and tablets.
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