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DSP Core for High-Volume, Cost-Sensitive Audio, Voice, and Baseband Applications

CEVA_teakliteIIThe CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based Harvard architecture, the CEVA-TeakLite family combines small die size, excellent code density, and high processing power.

CEVA-TeakLite-II block diagramThe second generation member of the CEVA-TeakLite family, the CEVA-TeakLite-II is a low-power, single MAC, 16-bit, 4-stage pipeline, fixed-point DSP core that has been specifically designed to be embedded in highly-integrated System-on-Chip (SoC) devices. The CEVA-TeakLite-II, is a fully synthesizable (soft core), process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency. Its small silicon footprint and low power make it ideal for cost-sensitive applications like low cost phones (cordless, wireless, VoIP), hands-free car kits, and headsets.

CEVA-TeakLite-II Supporting Deliverables

CEVA-TeakLite-II deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TeakLite-II designs can also be implemented in an FPGA for prototyping and system integration.

The CEVA-TeakLite-II is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’s DSP cores and Platform and Solutions. Visit our CEVAnet Partners page for more information.

CEVA-TeakLite-ll Target Applications

Target applications for the CEVA-TeakLite-II and Xpert-TeakLite-II sub-system include audio, voice, 2G/2.5G wireless baseband, Power Line Communications (PLC), VoIP, and other signal processing for mobile computing devices, wireless handsets, portable media players, hard disk drives, optical drives, and more.

Features Benefits
High performance
  • 620MHz @ 40nm G
high performance makes the CEVA-TeakLite-ll applicable to multiple application domains from audio and voice to baseband
Native 16-bit
  • Single-cycle 16x16-bit multiplier with double precision support
  • 36-bit ALU
  • Multiple 36-bit accumulation registers
Efficient signal processing, supported by a broad range of fully-certified voice and audio codecs
Easy software development
  • Optimizing C compiler
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • Tight MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market
...and many more - Download the CEVA-TeakLite-II Product Brief for more information


Architectural Highlights

Based on a 16x16-bit multiplier, the CEVA-TeakLite-ll can perform a Multiply-Accumulate (MAC) operation in a single cycle. The CEVA-TeakLite-ll also offers:

  • Up to 1MW program memory and 1MW data memory (16-bit words)
  • Two parallel 16-bit transfers to/from data memory
  • A 36-bit Arithmetic Logic Unit (ALU)
  • A 36-bit barrel-shifter
  • Four independent 36-bit accumulators
  • Automatic saturation on overflow
  • See the CEVA-TeakLite-ll Product Brief for more information

The CEVA-TeakLite-ll supports an advanced set of digital signal processing instructions as well as general-purpose microprocessor instructions. The CEVA-TeakLite-ll's instruction set and programming model are designed for the straightforward generation of compact and efficient code composed of only 16-bit wide instructions.

Support for up to 1MW (16-bit words) of program memory means that the CEVA-TeakLite-II can efficiently handle the large programs that are required when the core is used to handle both DSP and control functions. Similarly, support for up to 1MW (16-bit words) of data memory means that the CEVA-TeakLite-II can handle and process large data buffers. Dedicated mechanisms are implemented to support Real-Time Operating System (RTOS) requirements, such as nested loops and wide Automatic Context Switching.

The CEVA-TeakLite-ll is binary compatible with its predecessor, the widely adopted CEVA-TeakLite DSP core. This allows new designs to leverage existing applications and a large installed base of software; it also makes it easy for existing designs to be migrated to a higher performance core.

Codecs Available

Codecs available directly from CEVA include:

Vocoders Audio decoders Audio encoders
G.723 MP3 MP3
G.726 WMA8 SBC
G.727 SBC  
G.168 Dolby Digital (AC3)  
G.161 xxxxx    

Many other codecs and post-processing functions are available from our CEVAnet partners.

Related Platforms

Xpert-TeakLite-II functional block diagramThe Xpert-TeakLite-II sub-system augments the capabilities of the CEVA-TeakLite-II DSP core with a suite of pre-integrated hardware peripherals. Xpert-TeakLite-II incorporates various advanced features including on-chip program cache and data memories, a high-performance Direct Memory Access (DMA) controller, Buffered Time Division Multiplexing Ports (BTDMPs), Host I/F, and standard AMBA bridges (AHB and APB). Combining the CEVA-TeakLite-II core with off-the-shelf software provided by CEVA and its technology partners optimizes the Xpert-TeakLite-II for a variety of DSP-intensive applications, such as VoIP, audio, and voice.

The combination of the CEVA-TeakLite-II DSP core and the Xpert-TeakLite-II sub-system results in a complete solution, which significantly reduces risk and time-to-market. For example, the CEVA-TeakLite-II DSP core and the Xpert-TeakLite-II sub-system form the basis for CEVA-VoP, which is a complete VoIP hardware and software platform for VoIP phones and gateways.