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CEVA-TeakLite-4: A DSP Architecture for High-Performance, Low-Power Audio and Voice-Processing Applications

CEVA-TeakLite-4 DSP LogoThe CEVA-TeakLite Family of DSP cores is designed to address the needs of high volume, cost-sensitive markets. Founded on a classic memory-based architecture, the CEVA-TeakLite family combines small die size, high code density, and high processing power.

CEVA-TeakLite-4 DSP Family MembersThe fourth generation of the CEVA-TeakLite family, the CEVA-TeakLite-4 is a low-power, native 32-bit, variable 10-stage pipeline, fixed-point DSP architecture framework. The CEVA-TeakLite-4 is a fully synthesizable, process-independent design that allows the SoC designer to select the optimal implementation in terms of silicon area, power consumption, and operating frequency.

CEVA-TeakLite 4 Architecture-compliant Cores

The CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 DSP cores are based on, and compliant to, the high-performance, low-power CEVA-TeakLite-4 DSP architecture.

With a primary target of standalone audio DSP chips used to implement audio CODECs, audio D-Class amplifiers, and noise-reduction chips, the ultra-low-power CEVA-TL410 audio DSP core offers the smallest die size with its single 32x32-bit MAC, dual 16x16-bit MACs, and direct memory interface. If higher performance is required, the CEVA-TL411 audio DSP core provides dual 32x32-bit MACs and quad 16x16-bit MACs.

Alternatively, for CPU-centric SoCs, such as the application processors and main SoCs used in smartphones, digital televisions (DTVs), set-top boxes (STBs), and game consoles, the CEVA-TL420 audio DSP augments the features of the CEVA-TL410 with data and instruction cache controllers and a master/slave AXI system interface (the CEVA-TL421 augments the CEVA-TL411 with the same high-end capabilities). All CEVA-TeakLite-4 architecture-compliant cores are fully compatible with each other and with previous generation CEVA-TeakLite family cores.

An audio ISA (instruction set architecture) providing dedicated audio instructions is present in all CEVA-TeakLite-4-based cores. Also, all members of the family include an integrated, second-generation Power Scaling Unit (PSU 2.0) for smart power management.

The CEVA-TeakLite-4 architecture is scalable to support stand-alone audio/voice tasks such as filters, voice pre-processing, audio post-processing, and noise reduction; also for mobile applications such as off-loading the main CPU by performing multi-channel audio decode, transcoding, voice pre-processing, and audio post-processing under the Android or Windows 8 operating systems. The CEVA-TeakLite-4 architecture framework also supports user differentiation to allow expansion for handling proprietary algorithm acceleration and future use-cases.

CEVA-TeakLite 4 Supporting Deliverables

CEVA-TeakLite-4 block diagramThe CEVA-TL410, CEVA-TL411, CEVA-TL420, and CEVA-TL421 audio DSP cores are supported by a wide range of deliverables, which significantly reduces risk and time-to-market. These deliverables include a complete implementation along with associated hardware and software development tools and verification and simulation environments. CEVA-TeakLite-4-based designs can also be implemented in an FPGA for prototyping and system integration.

The CEVA-TeakLite-4 is also backed up by a wealth of software and algorithms. To further reduce the cost, complexity, and risk in bringing products to market, CEVA has established an ecosystem of partners who provide application software, reference designs, complementary IP, design services, and complete solutions based on CEVA’s DSP cores and Platforms and Solutions. Visit our CEVAnet Partners page for more information.

CEVA-TeakLite-4 Target Applications

Target applications for the CEVA-TeakLite-4 DSP cores are primarily audio and voice processing in mobile, home, and automotive products in chips ranging from the smallest, lowest-power audio CODECs, to application processors, to home audio, including digital televisions (DTVs), set-top boxes (STBs), game consoles, and more.

Features Benefits
Small size and ultra-low-power
  • 100K gates area optimized
CEVA-TeakLite-4 DSP cores can be used for applications that are highly sensitive to die-area and power consumption
High-performance
  • Up to 1.5 GHz @ 28nm HPM
CEVA-TeakLite-4 DSP cores support the toughest audio and voice use cases
Native 32-bit, Harvard/SIMD architecture DSP with multiple options:
  • 1/2/4 32x32-bit multipliers
  • 2/4 16x16-bit multipliers
  • 32-bit register file
  • Automatic 32-bit saturation
  • 72-bit MAC accumulation for wide dynamic range
  • Optional tightly-coupled instruction sets
Supported by a broad range of fully-certified HD-Audio and voice codecs
Easy software development
  • Optimizing C compiler
  • Cycle-accurate simulation and graphical profiling of the entire DSP sub-system
  • Macro assembler, linker, and GUI debugger
  • Tight MATLAB bi-directional connectivity (optional)
Smooth C-level software development and easy integration into target SoC reduces risk and time-to-market
...and many more – Download the CEVA-TeakLite-4 Product Brief

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Architectural Highlights

Based on a native 32-bit architecture, different members of the CEVA-TeakLite-4 family can perform one, two, or four 32x32-bit Multiply-Accumulate (MAC) operations and two or four 16x16-bit MAC operations in a single cycle. The CEVA-TeakLite-4 also offers:

  • Enhanced bit-manipulation capabilities for stream processing
  • Up to 5 operations executed in parallel - Dedicated single-precision and double-precision FFT instructions
  • Up to 4GW program memory and 4GW data memory (16-bit words)
  • L1 program memory (TCM or cache)
  • L1 data memory (TCM or 2-way, set-associative, hardware-configurable cache)
  • For more information, please contact info@ceva-dsp.com

The CEVA-TeakLite-4 architecture supports an advanced set of digital signal processing instructions as well as general-purpose microprocessor instructions. The CEVA-TeakLite-4's instruction set and programming model are designed for the straightforward generation of compact and efficient code.

The integrated second generation Power Scaling Unit (PSU 2.0) provides advanced power management including support for clock and voltage scaling.

All members of the CEVA-TeakLite-4 family are compatible with each other and are backward compatible with their predecessors, including the widely adopted CEVA-TeakLite, CEVA-TeakLite-II, CEVA-TeakLite-III, and CEVA-Teak DSP cores. This allows new designs to leverage existing applications and a large installed base of software; it also makes it easy for existing designs to be migrated to a higher performance core.

Codecs Available

Codecs available directly from CEVA include:

Vocoders Audio decoders Audio encoders Post-processing
G.723 MP3 MP3 Dolby Mobile 3+
G.729.1 MPEG4 AAC-LC MPEG4 AAC-LC Dolby ProLogic IIx
G.711 HE-AAC V1 HE-AAC V1 Dolby Volume
G.722 HE AAC V2 7.1 SBC DTS Extended Surround (ES)
AMR-NB xxx WMA10 Dolby Digital encoder (DDCE) DTS Neo:6
FR WMA10Pro DTS Transcoder  
AMR-WB RealAudio9    
SILK RealAudio10    
  SBC    
  Dolby TrueHD    
  Dolby Digital Plus    
  Dolby Digital (AC3)    
  Dolby MS10    
  Dolby MS11    
  DTS Master Audio    
  DTS High Resolution    
  DTS LBR    
  DTS 96/24    
  DTS Digital Surround    

Many other codecs and post-processing functions are available from our CEVAnet partners.

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